Analog design challenges and trade-offs using emerging materials and devices

Abstract

Analog device figures-of-merit change significantly with the introduction of advanced materials and devices such as high-k or Multiple-Gate FETs. Measurements show enhanced intrinsic gain and matching behavior for MuGFETs which help to reduce area and power consumption in analog circuits. However, high-k degrades matching, flicker noise and VT stability. Measured device performance is used to simulate the impact of these trends on circuit design trade-offs. Migrating from SiON to HfO2 dielectric approximately doubles area and power consumption to keep matching and noise performance constant. Transient VT instabilities in the range of 10mV can degrade the resolution of analog-to-digital converters by more than one bit. The use of non-binary ADCs is proposed to overcome these issues.

Impact of Gate Poly Depletion on Evaluation of Channel Temperature in Silicon-on-Insulator Metal–Oxide–Semiconductor Field-Effect Transistors with Four-Point Gate Resistance Measurement Method

“…However, in SOI MOSFETs, the increased channel temperature (T ch ) may decrease the reliability of the device and worse mobility as well as the drain current (I d ). 4,5) The increased T ch in SOI MOSFETs is due to the worse thermal conductivity of berried-oxide (BOX) layer (1.38 W K À1 m À1 ) than that of Si (148 W K À1 m À1 ). [6][7][8][9][10][11] To make a matters worse, in three-dimensional structures, the thermal resistance of a channel is expected to be much higher than that of planar SOI MOSFETs, since the thermal conductance of nanoscale Si decreases with a decrease in size.…”