Analysis and Design of a Dynamic Predistorter for WCDMA Handset Power Amplifiers

Yamanouchi, S.; Aoki, Yuuichi; Kunihiro, Kazuaki; Hirayama, Taku; Miyazaki, Takashi; Hida, H.

doi:10.1109/tmtt.2006.890515

Cited by 13 publications

(5 citation statements)

References 16 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…(19) shows that the APD needs to generate a third order component which has an opposite response respective to the proportional component generated by the PA to achieve the desired distortion cancellation. In PA design, this reversal in phase and magnitude can be translated to its AM-AM and AM-PM characteristics [15].…”

Section: Analog Pre-distortion Linearization (Apd)mentioning

confidence: 99%

“…As such is the implementation of the APD as a single HBT transistor with an independent biasing circuit to generate an opposite third order response [19]. Instead of using an energy hungry active device to accomplish the distortion cancellation, passive components are configured as a substitute, which improves the linear energy transmission of a class-E PA for WCDMA applications [20].…”

Section: Analog Pre-distortion Linearization (Apd)mentioning

confidence: 99%

See 1 more Smart Citation

Energy saving power amplifier design methodologies for mobile wireless communications

Eswaran

Ramiah

Kanesan

et al. 2015

Renewable and Sustainable Energy Reviews

View full text Add to dashboard Cite

Section: Analog Pre-distortion Linearization (Apd)mentioning

confidence: 99%

Section: Analog Pre-distortion Linearization (Apd)mentioning

confidence: 99%

Energy saving power amplifier design methodologies for mobile wireless communications

Eswaran

Ramiah

Kanesan

et al. 2015

Renewable and Sustainable Energy Reviews

View full text Add to dashboard Cite

“…Consequently, various linearization techniques have been employed to enhance the linearity of CMOS PAs and meet the EVM requirements of WLAN modulation signals. These techniques include the employment of MGTR (Multigated Transistors) [15,16], analog and digital predistortion technology [17][18][19], feedback and feedforward technology [20,21], and adaptive bias circuits [22]. The adoption of these techniques aims to mitigate linearity limitations and improve the overall performance of CMOS PAs so they can meet the stringent requirements of WLAN modulation signals.…”

Section: Introductionmentioning

confidence: 99%

A Fully Integrated High Efficiency 2.4 GHz CMOS Power Amplifier with Mode Switching Scheme for WLAN Applications

Shen

Taishan²,

Wu³

2023

Applied Sciences

View full text Add to dashboard Cite

A 3.3 V mode-switching RF CMOS power amplifier (PA) for WLAN applications is presented, which is integrated into a 55-nm bulk CMOS process. The proposed PA offers both static control and dynamic power control, allowing it to operate efficiently in both low-power and high-power modes. The pure low-power mode is achieved by reducing power cells, which are also used for linearization in high power mode. The low-power mode is achieved by reducing the number of power cells which are also used for linearization in the high-power mode. In the dynamic power control mode, the total AM–AM and AM–PM distortion is effectively compensated for by dynamically controlling the number of power cells and adjusting the matching input. The proposed PA achieves an output P1dB of 27.6 dBm with a PAE of 32.7% and an output P1dB of 17.7 dBm with a PAE of 10% in high-power and low-power modes, respectively. It is measured with an 802.11 n 64-quadrature-amplitude-modulation (MCS7) signal and shows a maximum average power of 19 dBm under an error-vector-magnitude (EVM) of −27 dB.

show abstract

“…The most promising solution to meet these demands is making the PA using a CMOS process. Furthermore, as the PA is co-integrated with other portions of the transceiver fabricated in the CMOS process, significant performance improvement can be achieved by utilizing baseband signal processing and Si-based on-chip linearization techniques [1][2][3][4][5][6][7][8][9][10][11]. However, it is challenging to integrate the PA into CMOS technology when the other blocks of the transceiver are already integrated.…”

Section: Introductionmentioning

confidence: 99%

Design of an Advanced CMOS Power Amplifier

Kim¹,

Park²,

Jin³

2015

Journal of electromagnetic engineering and science

View full text Add to dashboard Cite

The CMOS power amplifier (PA) is a promising solution for highly-integrated transmitters in a single chip. However, the implementation of PAs using the CMOS process is a major challenge because of the inferior characteristics of CMOS devices. This paper focuses on improvements to the efficiency and linearity of CMOS PAs for modern wireless communication systems incorporating high peak-toaverage ratio signals. Additionally, an envelope tracking supply modulator is applied to the CMOS PA for further performance improvement. The first approach is enhancing the efficiency by waveform engineering. In the second approach, linearization using adaptive bias circuit and harmonic control for wideband signals is performed. In the third approach, a CMOS PA with dynamic auxiliary circuits is employed in an optimized envelope tracking (ET) operation. Using the proposed techniques, a fully integrated CMOS ET PA achieves competitive performance, suitable for employment in a real system.

show abstract

Analysis and Design of a Dynamic Predistorter for WCDMA Handset Power Amplifiers

Cited by 13 publications

References 16 publications

Energy saving power amplifier design methodologies for mobile wireless communications

Energy saving power amplifier design methodologies for mobile wireless communications

A Fully Integrated High Efficiency 2.4 GHz CMOS Power Amplifier with Mode Switching Scheme for WLAN Applications

Design of an Advanced CMOS Power Amplifier

Contact Info

Product

Resources

About