Analysis of the effects of scaling on interconnect delay in ULSI circuits

Repairing plasma-damaged low-k HSQ films with trimethylchlorosilane treatment

“…This leads to the increase of the RC delay, which increases with scaling down and leads to various problems. This RC delay can be reduced by using Cu instead of Al (by approximately 35%), and by using inter-metal dielectric with dielectric constant k lower than that of SiO 2 (∼4), so called low-k dielectrics [1][2][3]. Replacement of SiO 2 by air (k∼1) and Al by Cu for the same circuitry can reduce RC delay by 75%.…”

Power dissipated by CMOS gates driving lossless transmission lines

“…This case has been thoroughly investigated and is well represented in the literature, e.g., [3]- [8]. The other limiting case is an LC transmission line where the resistance is negligible.…”

Delay and power expressions for a CMOS inverter driving a resistive-capacitive load

“…The area defined by this triangle is 1 2 I peak × t base , which models the total shortcircuit current I SC sourced by a CMOS inverter due to a non-step input [11].…”

“…Therefore, the integral of I SC is the area of a triangle, 1 2 base×height. In terms of the short-circuit current, the height can be modeled as I peak and the base can be modeled as t base (see Figure 5).…”

“…As the die size of CMOS integrated circuits continues to increase, interconnections have become increasingly significant [1]. With a linear increase in length, interconnect delay increases quadratically due to a linear increase in both interconnect resistance and capacitance [2].…”