Analysis on data retention time of nano-scale DRAM and its prediction by indirectly probing the tail cell leakage current

Abstract

Characteristics of the data retention time (tRET) of nano-scale DRAM have been described. In addition, new approaches to enhance tRET and their properties have been analyzed. To optimize the process, we developed the &ET-modeling methodology, which has a good agreement with experimental data. The key feature of the methodology is an indirect probing of the tail leakage current by fitting the leakage model to reproduce the measured characteristics of the retention. The model shows the GIDL current is a major factor determining tRET of 80nm RCAT technology.

Temperature-Adaptive Back-Bias Voltage Generator for an RCAT Pseudo SRAM

“…However, it also requires hidden refresh operations and lower standby current because it uses the SRAM interface. The recessed channel array transistor (RCAT) pseudo SRAM that has been generally used in recent years has the advantages of lower leakage and scalability compared to the planar transistor RAM [1]- [3]. Even though the RCAT process reduces the leakage drastically, it still has several kinds of leakage that should be considered to determine the data retention time.…”

“…They consist of the subthreshold leakage (I sub ) through the channel, the PN junction leakage from the cell node to the substrate, and the gate induced drain leakage (GIDL) that is caused by the strong electric field between the gate (biased low) and the drain (biased high). The p-n junction leakage is not a serious leakage source compared to the GIDL in the Samsung RCAT DRAM process [1].…”

“…They consist of the subthreshold leakage (I sub ) through the channel, the PN junction leakage from the cell node to the substrate, and the gate induced drain leakage (GIDL) that is caused by the strong electric field between the gate (biased low) and the drain (biased high). The p-n junction leakage is not a serious leakage source compared to the GIDL in the Samsung RCAT DRAM process [1].In the GIDL, if the voltage between the drain and the gate is kept low (such as 1.4 V), its leakage would constitute a small portion of the total leakage and doesn't significantly affect the retention time [7]. These two leakages determine the static The dynamic refresh time of the pseudo SRAM with frequent operations is determined by the subthreshold leakage (I sub ).…”