Architectures for finite Radon transform

Efficient reconfigurable architectures for 3D medical image compression

“…In addition to the summary of existing FRAT implementation on FPGA that have been discussed [71][72][73], [75], [76], Table 2.4 lists the important issues, such as the FPGA devices involved, programming approaches as well as the target applications. Virtex-E Handel-C and CoreGen Image processing [72] Virtex-II Handel-C Image processing [73] Virtex-E N/S Image processing [75] Virtex-II Verilog Image processing [76] Virtex-E Handel-C Image processing Note: N/S: Not stated…”

“…Virtex-E Handel-C and CoreGen Image processing [72] Virtex-II Handel-C Image processing [73] Virtex-E N/S Image processing [75] Virtex-II Verilog Image processing [76] Virtex-E Handel-C Image processing Note: N/S: Not stated…”

“…To overcome these restrictions, hardware implementation of FRAT is an interesting domain of study, especially for medical imaging application. Existing limited hardware implementation of the FRAT [71][72][73], [75], [76] in medical imaging application opens a huge gap to be filled. Finally, summary is given in Section 4.5.…”

An efficient VLSI architecture and FPGA implementation of the Finite Ridgelet Transform

“…Two architectures for the FRAT and their FPGA implementation has been described in [10]. The first architecture is called a ''Reference'' FRAT architecture and is a direct hardware implementation of a suitable modified variant of the standard FRAT pseudocode.…”

“…This reference architecture comprises an address logic initialiser, multiplexer, accumulators and two memory blocks for storing transform vectors. The second architecture in [10] is denoted as a ''Memoryless'' FRAT architecture which operates in a parallel manner and has with p times the throughput of the first architecture. Address logic initialiser, wide multiplexer and adder blocks are used as sub-blocks in this architecture.…”