2009
DOI: 10.1109/tcsii.2009.2019164
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Area-Efficient ESD-Transient Detection Circuit With Smaller Capacitance for On-Chip Power-Rail ESD Protection in CMOS ICs

Abstract: The RC-based power-rail electrostatic-discharge (ESD) clamp circuit with big field-effect transistor (BigFET) layout style in the main ESD clamp n-channel metal-oxidesemiconductor (NMOS) transistor was widely used to enhance the ESD robustness of a CMOS IC fabricated in advanced CMOS processes. To further reduce the occupied layout area of the RC in the power-rail ESD clamp circuit, a new ESD-transient detection circuit realized with smaller capacitance has been proposed and verified in a 0.13-μm CMOS process.… Show more

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Cited by 20 publications
(1 citation statement)
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“…The resistor-capacitor (RC) time constant in the power-rail ESD clamp circuit: on the one hand, it determined the magnitude of the biased gate voltage of M big , that is to control who dominates the current discharge process of the internal parasitic BJT transistor and the channel, thus affecting the robustness of M big . To bias the gate voltage of the M big , many circuits present ways to employ a resistor pair [3][4][5]; on the other hand, the RC time constant determines the response time of the M big , during the ESD event, it is necessary to ensure that the M big is turned on, but the RC time constant is too large, easy to cause mis-trigger and occupy a large area, so to avoid using excessive RC time constant, feedback delay techniques [6][7][8], multiple RC triggering [9,10], capacitive couple mechanism [11,12], hybrid triggered power clamp circuit [13,14], and current mirror structure amplifying capacitor [15,16] were proposed to provide solutions for power-rail ESD clamp circuit that reduce the RC time constant and prolong the response time of M big .…”
Section: Introductionmentioning
confidence: 99%
“…The resistor-capacitor (RC) time constant in the power-rail ESD clamp circuit: on the one hand, it determined the magnitude of the biased gate voltage of M big , that is to control who dominates the current discharge process of the internal parasitic BJT transistor and the channel, thus affecting the robustness of M big . To bias the gate voltage of the M big , many circuits present ways to employ a resistor pair [3][4][5]; on the other hand, the RC time constant determines the response time of the M big , during the ESD event, it is necessary to ensure that the M big is turned on, but the RC time constant is too large, easy to cause mis-trigger and occupy a large area, so to avoid using excessive RC time constant, feedback delay techniques [6][7][8], multiple RC triggering [9,10], capacitive couple mechanism [11,12], hybrid triggered power clamp circuit [13,14], and current mirror structure amplifying capacitor [15,16] were proposed to provide solutions for power-rail ESD clamp circuit that reduce the RC time constant and prolong the response time of M big .…”
Section: Introductionmentioning
confidence: 99%