Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144)
DOI: 10.1109/mwscas.2000.951618
|View full text |Cite
|
Sign up to set email alerts
|

Behavioral modeling and simulation of phase-locked loops for RF front ends

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
2
2
1

Citation Types

0
10
0

Publication Types

Select...
6
2
1

Relationship

0
9

Authors

Journals

citations
Cited by 22 publications
(10 citation statements)
references
References 2 publications
0
10
0
Order By: Relevance
“…Consequently, the simulated in-band noise floor in [9] shows a deviation from the measured results. In [11] a periodic steady state (PSS) analysis technique is used to capture CP gain mismatch noise in PLL systems. However, as pointed out in [9] this technique cannot be extended to Frac-N phase-locked-loop (PLL) systems as the Frac-N CP is operating with a time-varying nonperiodic duty cycle in the steady state.…”
Section: Introductionmentioning
confidence: 99%
“…Consequently, the simulated in-band noise floor in [9] shows a deviation from the measured results. In [11] a periodic steady state (PSS) analysis technique is used to capture CP gain mismatch noise in PLL systems. However, as pointed out in [9] this technique cannot be extended to Frac-N phase-locked-loop (PLL) systems as the Frac-N CP is operating with a time-varying nonperiodic duty cycle in the steady state.…”
Section: Introductionmentioning
confidence: 99%
“…The need for a behavioral level simulator is strengthened by the characteristic that both the PLL and the ∑-∆ modulator are nonlinear systems. In the literature many papers have studied the implementation of the behavioral models of classical PLL systems and ∑-∆ synthesizers [6][7][8]. However, there are few works that show the full analysis and design of ∑-∆ synthesizers using behavioral modeling.…”
Section: Introductionmentioning
confidence: 99%
“…Different behavioral models for PLL systems are presented for purely PLL simulation and verification [4][5][6][7]22]. A recent approach for hierarchical PLL design [17] focuses mainly on the jitter-power trade-off in the VCO design.…”
Section: Circuit Sizingmentioning
confidence: 99%