C4NP Lead Free Solder Bumping and 3D Micro Bumping

Busby, Jeremy T.; Dang, Bing; Gruber, P.; Hawken, D.; Shah, J.G.; Weisman, R.; Perfecto, Eric; Ruhmer, K.; Buchwalter, Stephen L.

doi:10.1109/asmc.2008.4529064

Cited by 11 publications

(12 citation statements)

References 6 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Finite element model was built according to a packaging component of 3-layer stacks of thinned TSV chips constructed using direct chip attach (DCA) by sequential reflow process [3,8], see Fig. 1 and Fig.…”

Section: A Finite Element Modelmentioning

confidence: 99%

See 1 more Smart Citation

Influence of geometry of microbump interconnects on thermal stress and fatigue life of interconnects in copper filled through silicon via structure

Yuwen

Zhou

et al. 2013

2013 14th International Conference on Electronic Packaging Technology

View full text Add to dashboard Cite

Through silicon via (TSV) is an emerging technology enabling three dimensional (3D) packaging through vertical interconnection between multiple chips, which can significantly increase I/O per unit area, reduce electrical resistance as well as RC delay, and miniaturize the solder interconnects. However, it can also dramatically increase the current density and thermal energy density in each interconnect meanwhile. Thus, the reliability of miniaturized interconnects should be paid more attention. In this study, the influence of geometry of microbump interconnects, in terms of standoff height (h) and contact angle ( ), on thermal stress and fatigue life of interconnects in TSV structures under thermal cycling loading conditions was investigated by finite element (FE) method.Simulation results show that high thermal stress (herein, the equivalent stress) zones locate at Cu/Si interfaces and microbump interconnects. Considering that interconnects are the weakest part in the packaging system, their thermal stress and thermal fatigue behaviors were further investigated, and results reveal that the microbump interconnects in the lower microbump interconnect array are more vulnerable compared with that in upper arrays, and the outmost microbump interconnects in each interconnect array are most dangerous during the thermal cycling load. Furthermore, the influences of both h and on the fatigue life of the dangerous microbumps were calculated by using the modified Darveaux's energy based method. Calculation results reveal that increasing decreasing h and increasing improve the fatigue life of microbump interconnects. Besides, the thermal stress has no necessary connection with fatigue life, whereas the thermal strain (which is influenced by the thermal stress, structure factors and triaxial stress state) is closely related to the plastic strain energy and should be taken into account in evaluation of fatigue life of solder microbump interconnects in TSV structures.

show abstract

Section: A Finite Element Modelmentioning

confidence: 99%

“…View of 2-layer and 3-layer stacks of thinned TSV Chips joined on a substrate by sequential reflow process[8].Fig. 3.…”

mentioning

confidence: 99%

Influence of geometry of microbump interconnects on thermal stress and fatigue life of interconnects in copper filled through silicon via structure

Yuwen

Zhou

et al. 2013

2013 14th International Conference on Electronic Packaging Technology

View full text Add to dashboard Cite

show abstract

“…10 illustrate the significant yield improvement over the last two years. [20,21] The yield data is derived from RVSI inspection of the 200 µm pitch product wafers. Yield learning model showed a 15% defect reduction per month since the start of the C4NP program.…”

Section: Wafer Bumping Yield Improvementsmentioning

confidence: 99%

C4NP for Pb-free solder wafer bumping and 3D fine-pitch applications

Shih

Dang

Gruber

et al. 2008

2008 International Conference on Electronic Packaging Technology &Amp; High Density Packaging

View full text Add to dashboard Cite

Controlled Collapse Chip Connection -New Process (C4NP) technology is a novel solder bumping technology developed by IBM to address the limitations of existing bumping technologies. Through continuous improvements in processes, materials and defect control, C4NP technology has been successfully implemented at IBM in the manufacturing of all 300mm Pb-free solder bumped wafers. Both 200 µm and 150 µm pitch products have been qualified and are currently ramping up volume production.Extendibility of C4NP to 50 µm ultra-fine pitch microbump application has been successfully demonstrated with the existing C4NP manufacturing tools. Targeted applications for microbumps are three-dimensional (3D) chip integration and the conversion of memory wafers from wirebonding (WB) to C4 bumping. The metrology data on solder volume, bump height, defect and yield have been characterized by RVSI inspection. This paper reviews the C4NP processes from mold manufacturing, solder fill and solder transfer onto 300 mm wafers, along with defect and yield analysis. Reliability challenges as well as solutions in the development and qualification of flip chip Pb-free solder joint are also reviewed. In addition to a suitable under bump metallurgy (UBM), a robust lead-free solder alloy with precisely controlled composition and special alloy doping is needed to enhance performance and reliability.

show abstract

“…Bump sizes range from around 500 m used in ball grid array (BGA) applications down to less than 50 m in microbump applications. 3D micro-bumping feasibility with 25 m solder bumps on 50 m pitch using C4NP has been demonstrated [1]. Accordingly, the electric current density in solder interconnects has increased dramatically, resulting in severe electromigration (EM) effect which leads to severe electromigration-related structural problems and defects such as microstructure coarsening, intermetallic compound (IMC) polarity or abnormal polarity growth, whiskers, hillocks and voids [2][3][4].…”

Section: Introductionmentioning

confidence: 99%

Interaction effect between electromigration and microstructure evolution in BGA structure Cu/Sn-58Bi/Cu solder interconnects

et al. 2014

2014 15th International Conference on Electronic Packaging Technology

View full text Add to dashboard Cite

Dimension of solder interconnects (or joints) and pitches has been continuously scaling down, resulting in inhomogeneous microstructure and severe electromigration (EM) effect in solder interconnects. In this study, the interaction effect between electromigration and microstructure evolution in ball grid array (BGA) structure Cu/Sn-58Bi/Cu solder interconnects under a direct current density of 1.5×10 8 A/m 2 is studied by cellular automaton (CA) modeling embedded with finite element (FE) simulation. Results show that, compared with configuration or geometry of BGA interconnects, the influence of inhomogeneous eutectic phases on the distribution of current density is more obvious. The current density in the Sn-rich phase is much higher than that in the Bi-rich phase. Bi atoms in Sn-rich phase are more prone to migrate to the anode first, rather than migrating directly along the interface between Bi-rich phase and Sn-rich phase. Consequently, the damage in the Sn-rich phase, rather than at phase interfaces or in the Bi-rich phase, could usually be observed in experiments. By employing the criterion of EM induced atomic flux of Bi in FE analysis under CA rules, simulation results of Bi-rich phase segregation are consistent with the experimental observation under current stressing.

show abstract

C4NP Lead Free Solder Bumping and 3D Micro Bumping

Cited by 11 publications

References 6 publications

Influence of geometry of microbump interconnects on thermal stress and fatigue life of interconnects in copper filled through silicon via structure

Influence of geometry of microbump interconnects on thermal stress and fatigue life of interconnects in copper filled through silicon via structure

C4NP for Pb-free solder wafer bumping and 3D fine-pitch applications

Interaction effect between electromigration and microstructure evolution in BGA structure Cu/Sn-58Bi/Cu solder interconnects

Contact Info

Product

Resources

About