Challenges of 29nm half-pitch NAND Flash STI patterning with 193nm dry lithography and self-aligned double patterning

Chiu, Ming-Chien; Lin, B. N.; Tsai, Meng‐Feng; Chang, Yu-Chieh; Yeh, Ming–Kung; Ying, Tzung-Hua; Ngai, Chris; Jin, Jaklyn; Yuen, Stephen; Huang, Sem; Chen, Yongmei; Miao, Liyan; Tai, Kevin; Conley, Amiad; Liu, Ian

doi:10.1117/12.804685

Cited by 15 publications

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“…Recent researches have demonstrated that within wafer CDU <2nm and LWR <2nm can be achieved for 30nm node NAND FLASH STI by positive SADP [1]. However, the characteristic of SADP also restricts the feasibility of specific pattern definition on the other hand.…”

Section: Introductionmentioning

confidence: 97%

Pattern decomposition and process integration of self-aligned double patterning for 30nm node NAND FLASH process and beyond

et al. 2009

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As IC manufacturing goes from 45nm to 30nm node half-pitch, the lithography process k1 factor will fall below 0.25 by using water-based ArF-immersion scanner. To bridge the gap between ArF-immersion and next generation lithography, which is not ready yet for production, Double Patterning Technology (DPT) has been evaluated and identified as a promising solution as it utilizes existing equipment and processes. Self Aligned Double Patterning (SADP) has the advantage of dense array definition without overlay issue and is hence useful for memory device; but its characteristic restricts the feasibility of two-dimensional circuit pattern definition on the other hand.This paper describes the ideas of 30nm node NAND FLASH cell circuit critical feature (pickup, gate, contact array) definition by decomposing the target patterns to SADP defined dense array in conjunction with cropping and/or periphery masks steps. The concerns and issues of cropping/periphery mask step process integration as well as SADP alignment algorithm are investigated, and the countermeasures with alternative process schemes and novel frame designs are presented. Finally, simulation prediction has shown that the capability of 30nm NAND FLASH critical features patterning with depth of focus equal to or above 0.15um is expected at each mask step by ArF-dry lithography.

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Section: Introductionmentioning

confidence: 97%

Pattern decomposition and process integration of self-aligned double patterning for 30nm node NAND FLASH process and beyond

et al. 2009

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“…[1]- [7] Double patterning (DP) technology is widely used for 30nm Half Pitch and below, because EUV technology is not ready for high volume manufacturing at this moment due to low EUV source power, poor PR LWR performances, and lack of EUV mask infrastructure. Figure 1 shows different kinds of DP technologies published in the literature [8]- [11] . Some of them, e.g.…”

Section: Introductionmentioning

confidence: 99%

Process requirements for pitch splitting LELE double patterning at advanced logic technology node

et al. 2012

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As IC dimensions continue to shrink beyond the 22nm node, optical single exposure cannot sustain the resolution required and various double patterning techniques have become the main stream prior to the availability of EUV lithography. Among various kinds of double patterning techniques, positive splitting pitch lithography-etch-lithographyetch (LELE) double patterning is chosen for printing complex foundry circuit designs. Tighter circuit CD and process margin control in such positive splitting pitch LELE double patterning process becomes increasingly critical especially for topography issues induced by the 1 st mask patterning with the 2 nd mask exposure. In this paper, laser parameters, topography issues with the 2 nd mask exposure, and SMO effects on CD performances are described in terms of the proximity CD portion of the scanner CD budget. Laser parameters, e.g. spectral shape and bandwidth, were input into the photolithography simulator, Prolith, to calculate their impacts on circuit CD variation. Mask-bias dependent lithographic performance was calculated and used to illustrate the importance of well-controlled laser performance parameters. Recommended laser bandwidth, mask bias and topography requirements are proposed, based on simulation results to ensure that the tight CD control (< 1nm) required for advanced technology node products can be achieved.

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“…8,9,10 Furthermore, it has the advantages of being implemented primarily with existing factory equipment and low capitol spending for development and volume manufacturing.…”

Section: Introductionmentioning

confidence: 99%

Implementing self-aligned double patterning on non-gridded design layouts

et al. 2009

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The Sidewall Spacer Double Patterning (SSDP) technique, also referred to as Self-Aligned Double Patterning (SADP), has been adopted as the primary double patterning solution for 32nm technology nodes and below for flash memory manufacturing. Many are now looking to migrate the technique to DRAM and random Logic layers. However, DRAM and especially Logic have far more complex layout requirements than NAND-FLASH, requiring a more sophisticated use of the SSDP technique. To handle the additional complexities an automated electronic design tool was used to calculate optimal layout splits of a design target into 2 or 3 masks. The model was programmed with immersion lithography and dry-193nm lithography MRC input rules and on wafer performance was tested. We discuss the patterning needs from the trim-mask and the pad-mask and associated lithography process window requirements and alignment accuracies necessary to pursue 32nm and 22nm half-pitch designs.

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Challenges of 29nm half-pitch NAND Flash STI patterning with 193nm dry lithography and self-aligned double patterning

Cited by 15 publications

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Pattern decomposition and process integration of self-aligned double patterning for 30nm node NAND FLASH process and beyond

Pattern decomposition and process integration of self-aligned double patterning for 30nm node NAND FLASH process and beyond

Process requirements for pitch splitting LELE double patterning at advanced logic technology node

Implementing self-aligned double patterning on non-gridded design layouts

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