Charge-based analytical model for the evaluation of power consumption in submicron CMOS buffers

Rosselló, Josep L.; Segura, J.

doi:10.1109/43.992767

Cited by 36 publications

(23 citation statements)

References 14 publications

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“…It can be observed that the presented analytical model for the evaluation of the overshooting time gives results close to those derived from SPICE simulations with 2.06% average error. Moreover, the prediction result of the model in [18] is not accurate compared with SPICE simulation with 19.72% average error.…”

Section: B Simulation Resultsmentioning

confidence: 99%

“…12 compares the overshooting time of the proposed method, SPICE simulation and the model in [18] with respect to various input signal transition times. Note that the model was proposed in [18] for CMOS gate power estimation, and was also used to predict CMOS gate delay time in [16]. In Fig.…”

Section: B Simulation Resultsmentioning

confidence: 99%

“…The value of C M in input high state consists of the side-wall capacitance of both transistors drain and the gate to drain overlap capacitance of NMOS transistor in the linear region [18] …”

Section: Modeling the Overshooting Effectmentioning

confidence: 99%

“…In [12], an expression was derived to compute the CMOS gate delay time while the step input delay time was required. In [18], an empirical model was proposed to estimate CMOS gate power consumption. However, these models are still not accurate enough in various conditions.…”

mentioning

confidence: 99%

“…In [9]- [16], the nonlinearity induced by the input-to-output coupling capacitance is taken into account for gate delay models. In [17], [18], the power consumption estimation models of CMOS buffers were given accounting for the influence of the input-to-output coupling capacitance in submicronmeter technologies. Since the overshooting time becomes one of important parameters for CMOS gate timing analysis or power consumption estimation, several empirical models have been proposed to estimate overshooting time.…”

mentioning

confidence: 99%

See 4 more Smart Citations

Modeling the Overshooting Effect for CMOS Inverter Delay Analysis in Nanometer Technologies

Huang

Kurokawa

Hashimoto

et al. 2010

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-With the scaling of complementary metal-oxidesemiconductor (CMOS) technology into the nanometer regime, the overshooting effect due to the input-to-output coupling capacitance has more significant influence on CMOS gate analysis, especially on CMOS gate static timing analysis. In this paper, the overshooting effect is modeled for CMOS inverter delay analysis in nanometer technologies. The results produced by the proposed model are close to simulation program with integrated circuit emphasis (SPICE). Moreover, the influence of the overshooting effect on CMOS inverter analysis is discussed. An analytical model is presented to calculate the CMOS inverter delay time based on the proposed overshooting effect model, which is verified to be in good agreement with SPICE results. Furthermore, the proposed model is used to improve the accuracy of the switch-resistor model for approximating the inverter output waveform.

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Section: B Simulation Resultsmentioning

confidence: 99%

Section: B Simulation Resultsmentioning

confidence: 99%

Section: Modeling the Overshooting Effectmentioning

confidence: 99%

mentioning

confidence: 99%

mentioning

confidence: 99%

See 3 more Smart Citations

Modeling the Overshooting Effect for CMOS Inverter Delay Analysis in Nanometer Technologies

Huang

Kurokawa

Hashimoto

et al. 2010

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Analysing the operation of the basic pass transistor structure

Nikolaidis

2006

Circuit Theory & Apps

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SUMMARYPass transistor logic has become important for the design of low-power high-performance digital circuits due to the smaller node capacitances and reduced transistors count it offers. However, the acceptance and application of this logic depends on the availability of supporting automation tools, e.g. timing simulators, that can accurately analyse the performance of large circuits at a speed, significantly faster than that of SPICE based tools. In this paper, a simple and robust modelling technique for the basic pass transistor structure is presented, which offers the possibility of fast timing analysis for circuits that employ pass transistors as controlled switches. The proposed methodology takes advantage of the physical mechanisms in the pass transistor operation. The obtained accuracy compared to SPICE simulation results is sufficient for a wide range of input and circuit parameters.

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A Compact Charge-Based Propagation Delay Model for Submicronic CMOS Buffers

Rosselló

Segura

2002

Lecture Notes in Computer Science

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Charge-based analytical model for the evaluation of power consumption in submicron CMOS buffers

Cited by 36 publications

References 14 publications

Modeling the Overshooting Effect for CMOS Inverter Delay Analysis in Nanometer Technologies

Modeling the Overshooting Effect for CMOS Inverter Delay Analysis in Nanometer Technologies

Analysing the operation of the basic pass transistor structure

A Compact Charge-Based Propagation Delay Model for Submicronic CMOS Buffers

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