Compact small-signal model for RF FinFETs

These last years, the triple-gate fin field-effect transistor (FinFET) has appeared as attractive candidate to pursue the complementary metal-oxide semiconductor technology roadmap for digital and analog applications. However, the development of analog applications requires models that properly describe the static and RF behaviors as well as the extrinsic parameters related to the three-dimensional FinFET architecture, in order to establish adequate design strategies. We demonstrate the feasibility of the compact model developed for symmetric doped double-gate metal-oxide-semiconductor field-effect transistor (symmetric doped double-gate MOSFET) to reproduce the experimental dc and RF behaviors for 40-nm technology node Silicon-on-Insulator triple-gate FinFETs. Extrinsic gate capacitances and access extrinsic resistances have been included in order to properly predict the transistor small-signal behavior, the current gain, and the maximum available power gain cut-off frequencies. Finally, the improvement of the FinFET RF characteristics by the reduction of the parasitics is addressed. Figure 13. Comparison between the modeled (lines) and experimentally obtained (dots) maximum oscillation frequency. Figure 14. Simulated maximum oscillation frequency vs. source/drain fin extension for several values of fin spacing. 476 A. G. MARTINEZ-LOPEZ ET AL.

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“…From the mobile charge and the drain current , the normalized total gate charge is calculated by

\begin{matrix} center \\ center q_{g} & center = \frac{4 W^{2} μ C_{italicox}^{, 2} ϕ_{t}^{3}}{I_{D S}} [\frac{1}{3} (q_{n s}^{3} - q_{n d}^{3}) + (q_{n s}^{2} - q_{n d}^{2}) - q_{b} (q_{n s} - q_{n d}) + q_{b}^{2} ln (\frac{q_{n s} + q_{b}}{q_{n d} + q_{b}})] \end{matrix}

…”

Section: Intrinsic Small‐signal Modelmentioning

confidence: 99%

“…When fin height ( H fin ) is higher than the fin width ( W fin ), the contribution of the lateral channels are dominant compared with the top one, allowing to use the SDDGM model . Also, it has been proven to properly reproduce the intrinsic RF parameters for long‐channel TG‐FinFETs .…”

Section: Introductionmentioning

confidence: 99%

RF modeling of 40‐nm SOI triple‐gate FinFET

Martinez-Lopez¹,

Cerdeira

Tinoco³

et al. 2014

Int J Numerical Modelling

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“…Another interesting application of SDDGM was done in the field of microwave transistors. A high-frequency compact analytical noise model for DG MOSFETs was obtained using the SDDGM DC model [48] and the compact small-signal model for RF FinFETs, where the high frequency equivalent circuit model parameters were extracted from de SDDGM DC model [49], [50]. Transconductance curves in linear and saturation regimes are shown in Fig.…”

Section: D) Sddgmmentioning

confidence: 99%

Review on double-gate MOSFETs and FinFETs modeling

et al. 2013

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“…In this context, a compact model with the aim to determine the DC and intrinsic RF parameters was demonstrated [4]. In order to provide high-quality SS-EC, there is an urgent need to accurately model the extrinsic capacitances which are strongly dependent on the FinFET geometry.…”

Section: Introductionmentioning

confidence: 99%

Fringing gate capacitance model for triple-gate FinFET

Salas

Tinoco

Martinez-Lopez

et al. 2013

2013 IEEE 13th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems

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In this paper, a semi-analytical extrinsic gate capacitance model for Triple Gate FinFET, based on threedimensional numerical simulations, is presented. The model takes into account the source/drain electrode and contact areas. It includes 5 capacitance components that describe the different fringing electrical couplings that exist inside the FinFET structure. The semi-analytical model accurately calculates the total extrinsic gate capacitance as function of the main geometrical parameters of Triple-Gate FinFET.

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Compact small-signal model for RF FinFETs

Cited by 5 publications

References 7 publications

RF modeling of 40‐nm SOI triple‐gate FinFET

RF modeling of 40‐nm SOI triple‐gate FinFET

Review on double-gate MOSFETs and FinFETs modeling

Fringing gate capacitance model for triple-gate FinFET

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