Fringing gate capacitance model for triple-gate FinFET

Salas, S.; Tinoco, J. C.; Martinez-Lopez, A. G.; Alvarado, J.; Raskin, J.-P.

doi:10.1109/sirf.2013.6489442

Cited by 8 publications

(6 citation statements)

References 5 publications

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“…The 2D model is actually rather 1.5D because it is not modeling the structure under a complete xy-plane. As to keep the naming consistent, it calls the conformal mapping as 2D model and a structural mapping as 3D model [5][6][7].…”

Section: Two-dimensional Analytical Modelmentioning

confidence: 99%

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The Analytical Models of Fringe Parasitic Capacitance of FinFET - A Review

Jiang

2024

J. Phys.: Conf. Ser.

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When planar MOSFET encounters its own scaling limit, FinFET was introduced and successfully replaced the traditional MOSFET. FinFET owns its privilege over the planar MOSFET for its high tolerance to short channel effect. However, due to FinFET’s 3D structure, high parasitic capacitance compared to planar MOSFET significantly degrades the transistor speed because of RC delay. This paper provides a review on the fringe capacitance of FinFET device based on the accuracy to experimental data of the two-dimensional and three-dimensional analytical models. Those models take the external and internal parasitic capacitance component into account. The three-dimensional model outperforms the two-dimensional model in levels of precision but requires more parameters and time to establish.

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Section: Two-dimensional Analytical Modelmentioning

confidence: 99%

“…Four basic types of capacitance component mapping are shown in figure 3. Detailed description of mathematical calculation is given in the paper presented by Salas et al [5] and all capacitance component could be concluded as follows:…”

Section: Typical Capacitance Structure In 2dmentioning

confidence: 99%

The Analytical Models of Fringe Parasitic Capacitance of FinFET - A Review

Jiang

2024

J. Phys.: Conf. Ser.

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“…As was described in [41][42][43], it is possible to define four basic capacitance structures: (i) parallel-plates, (ii) perpendicularplates or (iii) flat-plates non-parallel capacitor and (iv) fringing field capacitive component, as table 1 shows.…”

Section: Extrinsic Gate Capacitance Modelmentioning

confidence: 99%

“…There are three main possible options to reduce the total gate extrinsic capacitance: (i) varying the geometrical parameters, as was previously demonstrated for FinFET transistors [39,41]; (ii) by engineered source/drain contacts, as was demonstrated using faceted raised S/D contacts [44,45]; or (iii) reducing the spacer dielectric constant, as was previously demonstrated through air-gap spacers [46,47]. In order to define the possibility to minimize C gge by geometry optimization, the relative contribution of each external component has been analyzed, shown in figure 9.…”

Section: Gge Minimization For Nanometric Transistorsmentioning

confidence: 99%

Extrinsic gate capacitance compact model for UTBB MOSFETs

Martinez-Lopez

Tinoco

Lezama

et al. 2017

Semicond. Sci. Technol.

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Ultra-thin body and buried oxide transistors have gained attention as candidates for near future CMOS technology nodes. Recent studies have pointed out that the total parasitic gate capacitance becomes an important concern for very-high frequency performance. In this paper a semi-analytical model to describe the total extrinsic gate capacitance for ultrathin silicon body and buried oxide transistors is presented. The developed model considers the main technological parameters and has been verified by finite-element numerical simulations as well as by comparison with experimental measurements. The relative weight of the main parasitic components is addressed as well as their impact over the current gain cut-off frequency. Finally, the possibility to improve the cut-off frequency by about 35% due to the reduction of the parasitic gate capacitance is highlighted.

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“…In , on the basis of the device wideband measurements and 3D numerical simulations, as well as semi‐analytical expressions in , we analyzed the impact of the extrinsic capacitances on the FinFET RF behavior and propose some design guidelines to minimize the impact of those parasitic elements.…”

Section: Finfetsmentioning

confidence: 99%

Silicon‐on‐insulator MOSFETs models in analog/RF domain

Raskin

2013

Int J Numerical Modelling

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SUMMARYSeveral physical phenomena specific to silicon-on-insulator metal-oxide-semiconductor field-effect transistors, such as floating body effects, self-heating, and substrate coupling, are described and modeled. Small-signal equivalent circuit of ultra-thin body and thin buried oxide and fin field effect transistor (FinFET) are extracted, and their radio frequency figures of merit as well as their advantages and limitations are presented. We demonstrate the importance of performing wideband characterization at the early stage of the technology development in order to identify the device weaknesses and come up with technological solutions to overcome those. With the ongoing downscaling of the metal-oxide-semiconductor devices, the surrounding of the transistor, that is, the contacts, the access lines, and the substrate, starts to play a major role on the transistor behavior. There is an urgent need to develop adequate models for the new generation of devices valid over a wide frequency band.

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Fringing gate capacitance model for triple-gate FinFET

Cited by 8 publications

References 5 publications

The Analytical Models of Fringe Parasitic Capacitance of FinFET - A Review

The Analytical Models of Fringe Parasitic Capacitance of FinFET - A Review

Extrinsic gate capacitance compact model for UTBB MOSFETs

Silicon‐on‐insulator MOSFETs models in analog/RF domain

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