Correlating drain junction scaling, salicide thickness, and lateral NPN behavior, with the ESD/EOS performance of a 0.25 μm CMOS process

Amerasekera, A.; McNeil, V.M.; Rödder, M.

doi:10.1109/iedm.1996.554123

Cited by 39 publications

(10 citation statements)

References 1 publication

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“…For the parasitic bipolar device of a GGNMOS, V BE is equal to the substrate potential V sub [3]. Hence, the current distribution of the GGNMOS during the ESD zapping event can be evaluated if the substrate potential is obtained [4].…”

Section: A Test Patternmentioning

confidence: 99%

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The failure mechanism re-investigation Of ESD device on EPI wafer

Lee¹,

Kung²,

Kung³

et al. 2012

2012 IEEE International Reliability Physics Symposium (IRPS)

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The ESD failure mechanism of the EPI wafer device is reinvestigated, which is caused by the low substrate resistance induced transient current crowding. We also demonstrate that putting the ESD device in the deep-NWell (DNW) can effectively eliminate the low substrate resistance effect because the device in the DNW can be isolated from the P+ substrate. The DNW can not only improve the HBM and MM threshold voltages for EPI wafer device but also improve the CDM threshold voltage for EPI wafer and bulk wafer devices. Keywords-component; Human-body Model (HBM), Machine Model (MM), Charged-device model (CDM) style;

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Section: A Test Patternmentioning

confidence: 99%

“…This is the traditional model to explain why the EPI wafer worsens the device ESD performance [2], [3]. If this was true, the device should be unable to get the same I t2 regardless of what types of wafers it fabricated.…”

Section: Introductionmentioning

confidence: 97%

The failure mechanism re-investigation Of ESD device on EPI wafer

Lee¹,

Kung²,

Kung³

et al. 2012

2012 IEEE International Reliability Physics Symposium (IRPS)

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“…As the channel length of MOSFETs has been scaled down to sub-0.1 μm, the ultra-shallow source/drain (S/D) junction depth has been required to suppress short channel effects (SCEs) [1][2][3]. However, ultra-shallow S/D junction increases the sheet resistance (R sh ), which can degrade device performance [4].…”

Section: Introductionmentioning

confidence: 99%

A Study of the Dependence of Effective Schottky Barrier Height in Ni Silicide/n-Si on the Thickness of the Antimony Interlayer for High Performance n-channel MOSFETs

Lee¹,

Li²,

Oh³

et al. 2015

JSTS:Journal of Semiconductor Technology and Science

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Abstract-In this paper, the effective electron Schottky barrier height (Ф Bn ) of the Ni silicide/nsilicon (100) interface was studied in accordance with different thicknesses of the antimony (Sb) interlayer for high performance n-channel MOSFETs. The Sb interlayers, varying its thickness from 2 nm to 10 nm, were deposited by radio frequency (RF) sputtering on lightly doped n-type Si (100), followed by the in situ deposition of Ni/TiN (15/10 nm). It is found that the sample with a thicker Sb interlayer shows stronger ohmic characteristics than the control sample without the Sb interlayer. These results show that the effective Ф Bn is considerably lowered by the influence of the Sb interlayer. However, the current level difference between Schottky diodes fabricated with Sb/Ni/TiN (8/15/10 nm) and Sb/Ni/TiN (10/15/10 nm) structures is almost same. Therefore, considering the process time and cost, it can be said that the optimal thickness of the Sb interlayer is 8 nm. The effective Ф Bn of 0.076 eV was achieved for the Schottky diode with Sb/Ni/TiN (8/15/10 nm) structure. Therefore, this technology is suitable for high performance n-channel MOSFETs.Index Terms-Nckel silicide, antimony interlayer, Schottky diode, effective Schottky barrier height, nchannel MOSFETs

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“…During the late 1990s, the importance of electrical effects other than those of the intrinsic devices and gate delays, especially the role of interconnect and substrate parasitics, became a major concern. Earlier generation reliability issues for CMOS have shifted to the role of electro-static discharge (ESD) and its interrelationship with I/O circuit scaling [13]. These parasitic effects require characterization of both electrical and thermal behavior.…”

Section: Technology Scaling and Evolution Of Tcadmentioning

confidence: 99%

“…Many of the parasitic effects discussed above [13], [19] involve complex operating regimes with multipath, coupled phenomena. Multidevice computations and immersion-like visualization as depicted in Fig.…”

Section: Technology Scaling and Evolution Of Tcadmentioning

confidence: 99%

Perspectives on technology and technology-driven CAD

Dutton

Strojwas

2000

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-Computer-aided design (CAD) techniques are absolutely essential to harness the ever-increasing complexity of the microsystem design. Similarly, the technology CAD (TCAD) tools played a key role in the development of new technology generations. Although there is a common belief that the TCAD tools have been trailing the technology development, the situation has been changing very significantly especially over the last decade. For the deep submicrometer (DSM) devices, these tools provide a better insight than any measurement techniques and they have become indispensable in the new device creation. Moreover, these tools after calibration to a relatively small number of experiments, exhibit very impressive predictive power, which is utilized to speed up the technology integration and transfer to volume manufacturing. This results in very manufacturable high-yielding products that can be ramped up much faster than in the past decade, which is absolutely necessary given the huge costs of integrated circuit fabrication lines, short product lifecycles and penalties for being late to the market place. In this paper, we will present our perspective on the semiconductor technology development, and highlight the rapid growth of TCAD and its strategic use in semiconductor industry.

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Correlating drain junction scaling, salicide thickness, and lateral NPN behavior, with the ESD/EOS performance of a 0.25 μm CMOS process

Cited by 39 publications

References 1 publication

The failure mechanism re-investigation Of ESD device on EPI wafer

The failure mechanism re-investigation Of ESD device on EPI wafer

A Study of the Dependence of Effective Schottky Barrier Height in Ni Silicide/n-Si on the Thickness of the Antimony Interlayer for High Performance n-channel MOSFETs

Perspectives on technology and technology-driven CAD

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