Cu/Sn microbumps interconnect for 3D TSV chip stacking

Agarwal, Rahul; Zhang, Wenqi; Limaye, Paresh; Labie, Riet; Dimčić, Biljana; Phommahaxay, Alain; Soussan, Philippe

doi:10.1109/ectc.2010.5490698

Cited by 85 publications

(25 citation statements)

References 8 publications

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“…In order to further decrease the process temperature, bonding can also be achieved below the solder melting temperature by solid interdiffusion which is called SMB (Solid Metal Bonding) [3]. Due to the lower bonding temperature, the resulting joint is not completely transformed into intermetallic.…”

Section: Introductionmentioning

confidence: 99%

Reliability testing of Cu-Sn intermetallic micro-bump interconnections for 3D-device stacking

Labie

Limaye

Kw³

et al. 2010

3rd Electronics System Integration Technology Conference ESTC

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In this work, two different reliability experiments, thermal cycling and electromigration, are performed on fully packaged Si-to-Si stacks bonded with Cu-Sn intermetallic (IMC) micro-bumps. These experiments investigate both the more critical thermo-mechanical behavior as well as the expected positive thermalelectrical behavior. The Cu-Sn IMC bumps survive thermal cycling for more than 3900 cycles between -40 and 125 o C with 1 hour per cycle. The resistance to electromigration is strongly dependant on the used Sn thickness and shows an improved performance for thinner Sn samples (3.5µm) compared to thicker Sn (8µm). In either case, IMC bumps outperform standard solder flip chip bumps.

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Section: Introductionmentioning

confidence: 99%

Reliability testing of Cu-Sn intermetallic micro-bump interconnections for 3D-device stacking

Labie

Limaye

Kw³

et al. 2010

3rd Electronics System Integration Technology Conference ESTC

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show abstract

“…One of the key challenges in 3D integration is the fine pitch interconnection scheme, which has to accommodate various thermal and mechanical constraints, especially for the non-Si elements in the future 3D integrated package [2]. For advanced 3D stacking, various interconnection schemes and process technology have been proposed and most of them require a temperature higher than 250 °C and the underfill process during the bonding process [3,4]. As an alternative, anisotropic conductive film (ACF) can be a low-temperature, low-cost fine-pitch interconnection solution for future 3D integration.…”

mentioning

confidence: 99%

Study of fine pitch micro-interconnections formed by low temperature bonded copper nanowires based anisotropic conductive film

Tao

Mathewson

Razeeb

2014

2014 IEEE 64th Electronic Components and Technology Conference (ECTC)

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In this paper, Cu nanowire based anisotropic conductive film (ACF) has been systematically investigated in terms of its fine-pitch potential, electrical/ mechanical properties, process related issues and failure mechanisms. A test chip module including daisy-chain and 4-point structures was fabricated by electroplating and photolithography process, which has 160, 80, 40 and 30 µm bond pad pitches. The selection of membrane templates and the template based open/short failures have been discussed. Bond pads were finished with electroplated In to lower the bonding temperature and contact resistance. The electrical and mechanical performance of the interconnections has been studied in term of bonding force. The interconnect resistance of various pad sizes was 0.3-0.6 Ω per pad at the low bonding force of 1.5 N and dropped to 0.02-0.04 Ω per pad at the high bonding force of 10 N. The influence of bonding pressure on such nanowires formed interconnects was studied by microsectional analysis. For all pitch sizes, the electrical insulation was maintained for an applied voltage of 20 V. A shear strength of 1-5 MPa was achieved as a function of the bonding force and the fractural surface analysis verifies the Cu-In joint formed in such interconnections. IntroductionThe fabrication of stacked and vertically interconnected device layers (3D integration) with through Si via (TSV) technology [1] has provided a path to system scaling and performance enhancement. One of the key challenges in 3D integration is the fine pitch interconnection scheme, which has to accommodate various thermal and mechanical constraints, especially for the non-Si elements in the future 3D integrated package [2]. For advanced 3D stacking, various interconnection schemes and process technology have been proposed and most of them require a temperature higher than 250 °C and the underfill process during the bonding process [3,4]. As an alternative, anisotropic conductive film (ACF) can be a low-temperature, low-cost fine-pitch interconnection solution for future 3D integration. The conventional ACF, composed of randomly dispersed conductive micro particles in an adhesive polymer matrix, faces agglomeration problem when the size is reduced, resulting in potentially unstable electrical properties [5]. Moreover, the micro particles in the film have to be deformed to create electrical contact with high pressure, which constrains the minimum pitch size to ~ 100 µm for most commercial ACFs [6]. In order to further relax the thermal and mechanical constraints of interconnection process, nanowire based ACF (NW-ACF), containing metallic nanowire arrays vertically distributed in a porous polymer template, has been proposed as a low-temperature

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“…Characterization of micro-bumps for silicon carrier applications was carried out by Wright et al [52], who concluded that contact resistance was found to be about the same for eutectic SnPb as well as SnCu solder compositions, and at most 2-3 times larger than the standard 100 µm bumps. Further work in this field has been conducted by others [53][54][55]. Thus, although microbumps are not mandated for all 3D die stacking, their importance will increase in proportion to the requirement of having a tightly packed grid of interconnections between opposing die.…”

Section: Micro Bump Technologymentioning

confidence: 94%

3D integration review

Farooq¹,

Iyer²

2011

Sci. China Inf. Sci.

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3-D integration delivers value by increasing the volumetric transistor density with the potential benefit of shorter electrical path lengths through use of the shorter third dimension. Several researchers have studied various aspect of 3Di such as bonding level, through silicon via processes and integration, thermomechanical reliability of the vias, and the impact of the vias on devices. In this paper, we review some of the literature with a view to understanding the key options and challenges in 3Di. We also discuss some important applications of this technology, and the constraints that have to be overcome to make it work.

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Cu/Sn microbumps interconnect for 3D TSV chip stacking

Cited by 85 publications

References 8 publications

Reliability testing of Cu-Sn intermetallic micro-bump interconnections for 3D-device stacking

Reliability testing of Cu-Sn intermetallic micro-bump interconnections for 3D-device stacking

Study of fine pitch micro-interconnections formed by low temperature bonded copper nanowires based anisotropic conductive film

3D integration review

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