Datapath Synthesis for Standard-Cell Design

Zimmermann, R.

doi:10.1109/arith.2009.28

Cited by 14 publications

(7 citation statements)

References 8 publications

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“…This is due to the optimizations performed by Synopsys Design Compiler, which works at lower abstraction levels, (use of carry-save representation, high radix Booth recoding, conversion from Sum of Product to Product of Sum, etc.) [14]. These optimizations can produce unexpected results with unconventional arithmetic such as that in Eq.…”

Section: Discussionmentioning

confidence: 99%

Low Complexity Concurrent Error Detection for Complex Multiplication

Pontarelli

Reviriego

Bleakley

et al. 2013

IEEE Trans. Comput.

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Section: Discussionmentioning

confidence: 99%

Low Complexity Concurrent Error Detection for Complex Multiplication

Pontarelli

Reviriego

Bleakley

et al. 2013

IEEE Trans. Comput.

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“…The Baugh-Wooley method can be used for signed partial product generations [2]. This scheme is good for small word lengths of 8-16 bits [15].…”

Section: Figure 3: Partial Product Generatorsmentioning

confidence: 99%

“…To exploit the underly regularity of a synthesized arithmetic datapath, the proposed methodology structurally places 1 A commercial logic synthesis tool synthesizes arithmetic operations in an RTL code into a standard-cell netlist using dedicated datapath generators [15]. 2 We use "extraction" and "inference" interchangeably throughout the paper.…”

Section: Structural Placement Flow For a Synthesized Parallel Multipliermentioning

confidence: 99%

“…This method exploits inherent regularity in the synthesized netlist after passing through local cell regularity destroying logic minimization and technology mapping [6], where it is likely to have sufficient inherent regularity to benefit from it using structural placement especially for arithmetic circuits [7]. Unlike other indirect logic cell similarity based extraction methods, our method extracts inherent structure from the local regularity destroyed netlist by using explicit structural information and the primary input and primary output nets of the multiplier, which are considered to be provided by dedicated datapath generators in a logic synthesis tool [15] 1 . We extract and structurally place only a few structurally significant portions of the multiplier, which are the parts of the partial product generator and final carry propagating adder.…”

Section: Introductionmentioning

confidence: 99%

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Coarse-grained Structural Placement for a Synthesized Parallel Multiplier

Bae

Kim

Choi

et al. 2015

Proceedings of the 2015 Symposium on International Symposium on Physical Design

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We propose a new coarse-grained structural placement methodology tightly coupled with logic synthesis to exploit inherent structure of a synthesized parallel multiplier. The proposed method takes advantage of both benefits of logic optimizations and remaining regularity in the synthesized netlist. This is achieved by using a structural template of the multiplier, which is considered to be provided by dedicated datapath generators in the logic synthesis. The template includes primary input and output nets and structural specification of the multiplier, which is used to infer structural relative locations of a partial netlist and then structurally map the partial cells to guide structural placement of the rest of the module. Comparing to a conventional P&R (Place and Route) methodology, it improves the critical path delay, the total negative slacks, and the total wirelength by 2%, 42%, and 2%, respectively, on datapath intensive industrial designs.

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“…Modern microprocessors and embedded systems contain datapaths modules which play an important role in computations. Traditionally, datapath synthesis for standard-cell design goes through a series of steps, including extraction of arithmetic operations from RTL code, high-level synthesis (HLS), logic synthesis, and technology mapping [1]. The arithmetic operations such as addition, multiplication, shifting, comparison, and etc., are extracted first and are modeled into the datapaths.…”

Section: Introductionmentioning

confidence: 99%

DAG-aware logic synthesis of datapaths

Ciesielski

Choudhury

et al. 2016

Proceedings of the 53rd Annual Design Automation Conference

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Traditional datapath synthesis for standardcell designs go through extraction of arithmetic operations from the high-level description, high-level synthesis, and netlist generation. In this paper, we take a fresh look at applying high-level synthesis methodologies in logic synthesis. We present a DAG-Aware synthesis technique for datapaths synthesis which is implemented using And-Inv-Graphs. Our approach targets area minimization. The proposed algorithm includes identifying vector multiplexers, searching for common specification logic, and reallocating multiplexers in the Boolean network. We propose an algorithm to identify common specification logic by using subgraph isomorphism. Experimental results show that our technique can provide over 10% area reduction beyond the traditional design flow. The proposed algorithm is tested on industry designs and academic benchmark suits using IBM 14nm technology.

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Datapath Synthesis for Standard-Cell Design

Cited by 14 publications

References 8 publications

Low Complexity Concurrent Error Detection for Complex Multiplication

Low Complexity Concurrent Error Detection for Complex Multiplication

Coarse-grained Structural Placement for a Synthesized Parallel Multiplier

DAG-aware logic synthesis of datapaths

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