Design and Analysis of A 5.3-pJ 64-kb Gated Ground SRAM With Multiword ECC

Jahinuzzaman, Shah M.; Shah, Jaspal Singh; Rennie, D.; Sachdev, Manoj

doi:10.1109/jssc.2009.2021088

Cited by 20 publications

(8 citation statements)

References 13 publications

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“…In this technique a linear energy saving is achieved when the number of used columns is progressively reduced. Instead, we propose to use such dropped bits as check bits of a selective error-correction code (ECC) that protects only MSBs, as opposed to traditional ECC schemes that equally protect all bit positions with extra check bits [22]. Intuitively, strengthening MSBs through the unused LSBs makes the quality degradation more graceful and permits to down-scale voltage more aggressively with quadratic energy benefit.…”

Section: B Selective Error Correction Codementioning

confidence: 99%

“…6 shows an example where a read error occurs at bit under the proposed selective ECC scheme. The proposed technique entails the insertion of the simple logic implementing the Hamming code (24 XOR gates) without requiring any memory array modification, as opposed to traditional ECC that is based on the insertion of redundant columns [22]. The proposed technique can also be jointly adopted with a traditional ECC code, adding further protection against failures.…”

Section: B Selective Error Correction Codementioning

confidence: 99%

“…7, bit dropping is implemented in the bitline precharge circuit by adding a drop signal, which disables the precharge circuit and connects the bitline pair to ground, thus saving dynamic energy. Table I summarizes the advantages of the proposed selective techniques over prior art [7], [12], [14], [16], [22].…”

Section: B Selective Error Correction Codementioning

confidence: 99%

See 2 more Smart Citations

SRAM for Error-Tolerant Applications With Dynamic Energy-Quality Management in 28 nm CMOS

Frustaci

Khayatzadeh

Blaauw

et al. 2015

IEEE J. Solid-State Circuits

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In this paper, a voltage-scaled SRAM for both error-free and error-tolerant applications is presented that dynamically manages the energy/quality trade-off based on application need. Two variation-resilient techniques, write assist and Error Correcting Code, are selectively applied to bit positions having larger impact on the overall quality, while jointly performing voltage scaling to improve overall energy efficiency. The impact of process variations, voltage and temperature on the energy-quality tradeoff is investigated. A 28 nm CMOS 32 kb SRAM shows 35% energy savings at iso-quality and operates at a supply 220 mV below a baseline voltage-scaled SRAM, at the cost of 1.5% area penalty. The impact of the SRAM quality at the system level is evaluated by adopting a H.264 video decoder as case study.Index Terms-Error-tolerant, error-free, energy-quality tradeoff, ultra-low power processing, near-threshold, SRAM, approximate computing, resiliency.

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Section: B Selective Error Correction Codementioning

confidence: 99%

Section: B Selective Error Correction Codementioning

confidence: 99%

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SRAM for Error-Tolerant Applications With Dynamic Energy-Quality Management in 28 nm CMOS

Frustaci

Khayatzadeh

Blaauw

et al. 2015

IEEE J. Solid-State Circuits

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“…Pulses of this form were used to simulate single-and [20], and DICE [12] cells and the results are summarized in Table I.…”

Section: Soft Error Robustnessmentioning

confidence: 99%

A 32 kb Macro with 8T Soft Error Robust, SRAM Cell in 65-nm CMOS

Shah

Nairn

Sachdev

2015

IEEE Trans. Nucl. Sci.

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A 32-kb macro containing an eight-transistor soft error robust SRAM cell with differential read and write capabilities is presented. The 8T cell does not have dedicated access transistors, and its quad-latch configuration stores data on four interlocked storage nodes. The macro was designed in a 65-nm CMOS process. The cell demonstrates excellent read data stability down to 0.55 V and is well suited for low-voltage, low-power applications. Neutron radiation testing on the macro exhibits at least improvement in Failure in Time (FIT) rate compared with the conventional 6T SRAM cell in 65-nm CMOS technology. Index Terms-Hardened by design (HBD), single-event upset (SEU), soft-error rate (SER), soft-error robust, SRAM.

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“…This is an architectural solution, as the basic SRAM bit cell is not altered, rather the architecture of the SRAM array is altered. With ECC extra bits are added and the data is coded such that in the event of an error, the original data can be recovered [20]. An ECC architecture does not prevent errors, rather it compensates for errors when they occur.…”

Section: ) Architectural Solution: Eccmentioning

confidence: 99%

Design challenges in nanometric embedded memories

Rennie

Shakir

Sachdev

2009

2009 3rd International Conference on Signals, Circuits and Systems (SCS)

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Embedded memories comprise over half the die area in modern SOC ICs. These circuits enable large gains in performance, however they bring with them many challenges. As CMOS technology scales deep into the nano-metric region the size and density of embedded memories are increasing, both of which result in increased challenges for designers. This paper describes the design challenges intrinsic to the implementation of embedded memories in modern nanometric CMOS processes.

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Design and Analysis of A 5.3-pJ 64-kb Gated Ground SRAM With Multiword ECC

Cited by 20 publications

References 13 publications

SRAM for Error-Tolerant Applications With Dynamic Energy-Quality Management in 28 nm CMOS

SRAM for Error-Tolerant Applications With Dynamic Energy-Quality Management in 28 nm CMOS

A 32 kb Macro with 8T Soft Error Robust, SRAM Cell in 65-nm CMOS

Design challenges in nanometric embedded memories

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