Design and Fabrication of 4H–SiC Lateral High-Voltage Devices on a Semi-Insulating Substrate

Lee, Wen-Shan; Chu, K.R.; Chen, Huang-Chin; Lee, Lurng-Shehng; Tsai, Ming-Dar; Lee, Kung‐Yen; Zhao, Feng

doi:10.1109/ted.2011.2178028

Cited by 21 publications

(9 citation statements)

References 12 publications

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“…At the same time, the R on,sp decreases because, in this case, the W STI is fixed. Also, as the effective doping concentration is smaller at a larger K, the electric field is more uniformly distributed, which yields a higher BV, since the slope for the electric field is related to the net doping in the drift region [24]. The distribution of the electric field at position A beneath the surface of the silicon along the z-direction, as presented in Fig.…”

Section: DC Performance Of Hv Finfets Under High-k Dielectric Resurfmentioning

confidence: 99%

On the Effects of High-K Dielectric RESURF in High-Voltage Bulk FinFETs

Cheng

Lai

et al. 2020

IEEE J. Electron Devices Soc.

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High-K dielectric reduced surface field (RESURF) effects in high-voltage bulk FinFETs through three-dimensional simulation are discussed in this paper for the first time. Compared to a planar gate LDMOSFET where the length of the drift region is the same, dielectric RESURF significantly increases the optimal implant dose for the drift region to a higher value, although BV 2 /R on,sp is similar. By using a high-K dielectric in the shallow trench isolation (STI) to further enhance the dielectric RESURF, the BV is increased and the R on,sp is reduced, yielding a significantly improved BV 2 /R on,sp , together with a better ON/OFF current ratio. However, with the insertion of the high-K STI, C GD is increased and a punch-through in the drift region caused by the depletion region occurs at a smaller V DS , which is consistent with theory. It is observed that the high-K dielectric RESURF also has an impact on the vertical breakdown, and care must be taken to achieve an optimal BV. The simulation results presented in this paper are of great importance for realizing a system-on-a-chip (SOC) based on advanced CMOS technologies.

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Section: DC Performance Of Hv Finfets Under High-k Dielectric Resurfmentioning

confidence: 99%

On the Effects of High-K Dielectric RESURF in High-Voltage Bulk FinFETs

Cheng

Lai

et al. 2020

IEEE J. Electron Devices Soc.

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“…for a voltage of 320 V. The best configuration is C3 because the leakage current is at 1 mA for a voltage of 335 V. W. S. Lee has demonstrated on [10] that an increase of the thickness hp from the layer P of 5 µA to 20 µA allows to increase the breakdown voltage from 600 V to 2.4 kV. The C2 and C3 configurations indicate the presence of a plateau between 70 V and 100 V. A considered hypothesis will be a progressive depletion of the space charge area, which could be faster than in the configuration C1.…”

Section: Effect Of the Polarization Of The Backside Of The Wafer Omentioning

confidence: 99%

SiC lateral Schottky diode technology for integrated smart power converter

Mogniotte

Raynaud

Lazar

et al. 2018

2018 IEEE International Conference on Industrial Technology (ICIT)

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“…Third, vertical leakage is minimized, as the SOI layout does, making hightemperature operating possible. However, substrate-assisted depletion (SAD) is suppressed, due to the fact that no dopant in the SiC substrate can create the back-RESURF effect [15], [25] that are inherent in SOI and bulk-Si case. This vertical depletion can be positive or negative to devices' figure of merit, which depends on the RESURF dimension (2-D or 3-D).…”

Section: Simulated Si/sic Structuresmentioning

confidence: 99%

“…The doping in their drift regions are arranged in a way similar to [20], [22], with some modifications to suit the Si/SiC structure for 600 V. The detail on this for the SOI-like Si/SiC has been stated in [26] and [27], highlighting a linear doping profile with a dose half of that of the equivalent SOI transistor [28]. As for the bulk-Si-like Si/SiC, impurity concentrations of the N drift and P buried are determined based upon the triple RESURF principle [20], while the P-substrate doping is decided following the rule for lateral SiC-on-SI SiC power transistors [25]. These configurations result in the drift regions of both devices having similar doses of about 3 × 10 12 cm −2 [20] but they differ in doping concentration (cm −3 ) owing to dissimilar Si layer thickness.…”

Section: Simulated Si/sic Structuresmentioning

confidence: 99%

Comparative Study of RESURF Si/SiC LDMOSFETs for High-Temperature Applications Using TCAD Modeling

Chan

Sanchez

et al. 2017

IEEE Trans. Electron Devices

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2017) Comparative study of RESURF Si/SiC LDMOSFETs for high-temperature applications using TCAD modeling. IEEE Transactions on Electron Devices, 64 (9). pp. 3713-3718. Permanent WRAP URL:Abstract -This paper analyses the effect of employing an Si on semi-insulating SiC (Si/SiC) device architecture for the implementation of 600-V LDMOSFETs using junction isolation and dielectric isolation reduced surface electric field technologies for high-temperature operations up to 300°C. Simulations are carried out for two Si/SiC transistors designed with either PN or silicon-on-insulator (SOI) and their equivalent structures employing bulk-Si or SOI substrates. Through comparisons, it is shown that the Si/SiC devices have the potential to operate with an offstate leakage current as low as the SOI device. However, the low-side resistance of the SOI LDMOSFET is smaller in value and less sensitive to temperature, outperforming both Si/SiC devices. Conversely, under high-side configurations, the Si/SiC transistors have resistances lower than that of the SOI at high substrate bias, and invariable with substrate potential up to −200 V, which behaves similar to the bulk-Si LDMOS at 300 K. Furthermore, the thermal advantage of the Si/SiC over other structures is demonstrated by using a rectangle power pulse setup in Technology Computer-Aided Design simulations.Index Terms-High-temperature operation, Power LDMOSFETs, reduced surface electric field (RESURF), semiconductor device modeling, silicon carbide, siliconon-insulator technology, silicon-on-silicon carbide.

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Design and Fabrication of 4H–SiC Lateral High-Voltage Devices on a Semi-Insulating Substrate

Cited by 21 publications

References 12 publications

On the Effects of High-K Dielectric RESURF in High-Voltage Bulk FinFETs

On the Effects of High-K Dielectric RESURF in High-Voltage Bulk FinFETs

SiC lateral Schottky diode technology for integrated smart power converter

Comparative Study of RESURF Si/SiC LDMOSFETs for High-Temperature Applications Using TCAD Modeling

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