Design and fabrication of tilting and piston micromirrors for maskless lithography

Chen, Yijian; Chu, Chi Hui; Shroff, Yashesh; Wang, Jen-Shiang; Oldham, W.G.

doi:10.1117/12.599389

Cited by 7 publications

(21 citation statements)

References 0 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Fruitful technological advances had been made by various research teams, spanning a wide range of technical fields from system-level architecture, data compression and decompression, storage/interface circuit design, imaging strategy and optimization, [8][9][10][11][12][13][14][15][16][17][18][19][20][21][22][23][24][25][26] to dynamics, control and fabrication of micromirror devices. [27][28][29][30][31][32][33][34][35][36][37][38][39][40][41][42][43][44][45] Unfortunately, the university research funding dropped in a time frame of one to two years (2006)(2007), resulting in significantly slowed progress and even technological stagnation which were reflected in overall reduction of publication activity in projection maskless lithography after 2007. Although research teams from Micronic, ASML, Bell Lab, and Imec continued to make technical contributions, most of them were targeted at DUV wavelength.…”

Section: Introductionmentioning

confidence: 99%

“…46 In Fig. 1, we show a conceptual diagram of a NEMS based maskless EUV lithography system, 1,42,46 in which 10 8 to 10 9 nanomirrors are fabricated on a small chip (with a size of 2-3 cm) to achieve satisfactory throughput and resolution requirements. Each nanomirror consists of 40-50 Mo/Si multi-layers to effectively reflect EUV light, with total mirror thickness of about 0.3 μm.…”

Section: Introductionmentioning

confidence: 99%

“…The parallel-plate structure of nanomirrors is well known for suffering from the unstable "pull-in" problem. 33,42 More stable devices such as the vertical double-comb tilting nanomirrors and doubly clamped piston nanomirrors were proposed to avoid the instability problem. 42,46 The transient and resonant behavior of various types of electro-mechanically coupled microsystems with varying degrees of freedom have been investigated using perturbation method, linear control theory, and numerical simulation.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Past progress, current status, and future perspective of digital EUV lithography for high-resolution semiconductor manufacturing

Chen,

Song,

Gao

et al. 2024

Novel Patterning Technologies 2024

View full text Add to dashboard Cite

In this paper, a general review of the past progress, current status and future perspective of MEMS/NEMS based maskless EUV digital lithography for high-resolution semiconductor manufacturing is presented. Starting from the maskless patterning resolution and throughput requirements, we shall discuss the unique characteristics of digital EUV lithography spanning from optical and system-level design, imaging methodology, writing engine, to device process development and fabrication progress achieved. The wafer scan induced image blur impacts maskless writing speed and imaging strategy. The required high demagnification and redundant multiple-pulse exposure help to enable the defect-tolerant printing. Digital EUV lithography allows multiple/sequential stitching exposures in one scanning process without throughput penalty, thus can simplify the patterning process and amplify its competitiveness in high-NA application. Moreover, its grayscale/analog imaging principle not only significantly reduces the data rate but also provides an efficient way to enhance the resolution capability. Dynamics, control and design of electrically damped MEMS/NEMS devices will be examined. A low-temperature LPCVD SiGe process for MEMS/IC integration has been developed and the micromirror fabrication results will be reviewed. It is shown that reflective nanomirrors based maskless approach is one path to cost-effective and defect-tolerant compact EUV lithography, which helps to create emerging opportunities for low-volume but cutting-edge IC applications. Potential processing challenges and scaling issues of nanomirror device technology for a timely insertion of digital EUV lithography into future advanced IC manufacturing will also be discussed.

show abstract

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Past progress, current status, and future perspective of digital EUV lithography for high-resolution semiconductor manufacturing

Chen,

Song,

Gao

et al. 2024

Novel Patterning Technologies 2024

View full text Add to dashboard Cite

show abstract

“…The main characteristic of SAMP processes is the consecutive sidewall-spacer steps that enable spatial frequency multiplication. The fabrication technique to use spacers to pattern dense and fine features (e.g., transistor gates [33][34][35] and MEMS/NEMS devices [36][37][38]) dates back to several decades ago. As a density multiplication concept, it had been well known in our IC lithography/processing society for a long time despite some misunderstanding that it was invented just recently.…”

Section: Introductionmentioning

confidence: 99%

Benchmarking process integration and layout decomposition of directed self-assembly and self-aligned multiple patterning techniques

et al. 2014

Self Cite

View full text Add to dashboard Cite

In this paper, we present a benchmarking study of directed self-assembly (DSA) and self-aligned multiple patterning (SAMP) techniques for potential applications in manufacturing 10-nm (half-pitch) IC devices. Using the self-aligned quadruple patterning (SAQP) process as an example, we compare their process characteristics and complexity/costs, identify the integration challenges, and propose various patterning solutions for both BEOL and FEOL applications. Major differences in DSA and SAQP mask strategy, layout decomposition algorithm, and pattern-generation modeling are discussed, and critical requirements of overlay accuracy and CD control for implementing a DSA process in NAND wordline patterning are indentified. DSA technique is found to be a complementary solution for certain niche applications and we suggest that our industry should allocate more R & D resources to solve the 2-D SAMP layout decomposition challenges for logic BEOL patterning. We also propose an "out-of-the-box" idea of combining DSA and SADP process to significantly improve the 2-D design flexibility and develop a layout decomposition algorithm for this hybrid process.

show abstract

“…The 3tmx3gm polysilicon mirrors positioned to a minimum of 32 levels can achieve 22nm feature sizes with a Inm edge placement through a 140x optical reduction [6]. The mirrors can be either piston or tilting type [7][8], and the size of array requires the integration of driving electronics onto the SLM chip. Our design demonstrates the feasibility of an analog interface to the nanomirror array, capable of storing and maintaining precise voltage based position data between the laser flashes.…”

Section: Introductionmentioning

confidence: 99%

A 6-b DAC and Analog DRAM for a Maskiess Lithography Interface in 90 nm CMOS

Fang

Roberts

Nikolić

2006

2006 IEEE Asian Solid-State Circuits Conference

View full text Add to dashboard Cite

A parallel, 12gm-pitch, low-power 6-b segmented digital-to-analog converter (DAC) array drives an array of 3gm x 3gm analog DRAM cells in a 2.5/1V 90 nm CMOS process, with an application in maskless lithography. An innovative self-calibrating compensation circuit limits the effect of charge leakage and capacitive process mismatch to less than 0.5LSB over lOOms of data hold time. A 2mm x 2mm test chip implements a mixed-signal interface with 32 DACs driving four 32 x 256 analog DRAM arrays.

show abstract

Design and fabrication of tilting and piston micromirrors for maskless lithography

Cited by 7 publications

References 0 publications

Past progress, current status, and future perspective of digital EUV lithography for high-resolution semiconductor manufacturing

Past progress, current status, and future perspective of digital EUV lithography for high-resolution semiconductor manufacturing

Benchmarking process integration and layout decomposition of directed self-assembly and self-aligned multiple patterning techniques

A 6-b DAC and Analog DRAM for a Maskiess Lithography Interface in 90 nm CMOS

Contact Info

Product

Resources

About