Design and failure analysis of logic-compatible multilevel gain-cell-based dram for fault-tolerant VLSI systems

Abstract

This paper considers the problem of increasing the storage density in fault-tolerant VLSI systems which require only limited data retention times. To this end, the concept of storing many bits per memory cell is applied to area-efficient and fully logic-compatible gain-cell-based dynamic memories. A memory macro in 90-nm CMOS technology including multilevel write and read circuits is proposed and analyzed with respect to its read failure probability due to within-die process variations by means of Monte Carlo simulations.

A sub-V<inf>T</inf> 2T gain-cell memory for biomedical applications

“…Previously reported gain-cell cell topologies include either two or three transistors and an optional MOSCAP or diode [14]. While the basic two-transistor (2T) bitcell has the smallest area cost, it limits the number of cells which can connect to the same read bitline (RBL) due to leakage currents from unselected cells masking the sense current [14].…”

“…While the basic two-transistor (2T) bitcell has the smallest area cost, it limits the number of cells which can connect to the same read bitline (RBL) due to leakage currents from unselected cells masking the sense current [14]. However, as typical biomedical sensor nodes require only small memory arrays with relatively few cells per RBL, we consider the implementation of a sub-V T 2T bitcell as a viable option.…”

“…The resulting NMOS/PMOS gain-cell shown in Fig. 4 shares the n-well on three sides between neighboring cells [14] to keep the area cost low. The storage node capacitance is extended from 0.5 fF (primarily diffusion and gate capacitance) to 2.5 fF by metal stacking.…”

Refresh-free dynamic standard-cell based memories: Application to a QC-LDPC decoder

“…3(b) suffers from the body effect: its positive source-to-body voltage V SB increases its threshold voltage V T , which aggravates the readout process of an already deteriorated logic "1". Similarly to a common practice in gaincell eDRAM design [10], adding a coupling capacitor in form of a MOS capacitor (MCP) between the SN and the RWL, as shown in Fig. 3(c), was found to considerably improve the read "1" robustness of our bitcell, as well.…”

Replica bit-line technique for embedded multilevel gain-cell DRAM

“…Replacing conventional 1-transistor 1-capacitor (1T1C) DRAM cells with gain-cells leads to memory macros which are fully compatible with standard digital CMOS technologies [5], reduces cost, and allows for non-destructive read operation. An 8-kb multilevel gain-cell DRAM implemented in 90-nm CMOS technology has roughly half the area of a corresponding single-port SRAM macro, at the cost of a small percentage of read failures, due to within-die (WID) process variation, and limited retention time [5].…”