Design and synthesis of reconfigurable control-flow structures for CGRA

Rakossy, Zoltan Endre; Acosta-Aponte, Axel; Noll, Tobias G.; Ascheid, Gerd; Leupers, Rainer; Chattopadhyay, Anupam

doi:10.1109/reconfig.2015.7393298

Cited by 4 publications

(18 citation statements)

References 28 publications

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“…In the following exploration, methodology and early experimental results are presented, also published in [134].…”

Section: Importance Of Flexible Control Flowmentioning

confidence: 99%

“…To make CGRAs tackle larger applications, several solutions for the addition of control flow processing have been proposed in the past, discussed in the following [134].…”

Section: Background On Control-flow Processing In Cgrasmentioning

confidence: 99%

“…Taking 9 linear algebra kernels from Chapter 6 as the target application domain, 119 control-flow pieces of the Q-stage of Layers is analyzed, in order to extract how exactly control flow is processed and what kind of hardware resources, processing element types and interconnects may be needed to construct a reconfigurable control flow structure, presented in the following [134].…”

Section: Control Flow Analysis Of the Candidate Kernels Running On Lamentioning

confidence: 99%

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Modeling, analysis and exploration of layers: A 3D computing architecture

Rakossy

2014

2014 22nd International Conference on Very Large Scale Integration (VLSI-SoC)

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Current trends in architectural design require high-performance, low-power, flexible architectures that can adapt quickly onto the ever shifting and evolving application landscape. Finding the best architecture matching these stringent constraints is further limited by a short time-to-market window, which severely limits design exploration options. This work tackles these problems by proposing a different view on architectural flexibility, which can be exploited to achieve high energy-efficiency and performance instead of being traded off, by exploiting the advantages of reconfigurable architectures. Starting from a theoretical view, a methodology is produced for exploration of two different approaches in achieving high energy efficiency with two different architectural concepts: an architecture perfectly tuned to the application; and a new reconfigurable layered architecture, which can adapt its structure to match the application.

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“…In the following exploration, methodology and early experimental results are presented, also published in [134].…”

Section: Importance Of Flexible Control Flowmentioning

confidence: 99%

“…To make CGRAs tackle larger applications, several solutions for the addition of control flow processing have been proposed in the past, discussed in the following [134].…”

Section: Background On Control-flow Processing In Cgrasmentioning

confidence: 99%

Section: Control Flow Analysis Of the Candidate Kernels Running On Lamentioning

confidence: 99%

See 1 more Smart Citation

Modeling, analysis and exploration of layers: A 3D computing architecture

Rakossy

2014

2014 22nd International Conference on Very Large Scale Integration (VLSI-SoC)

Self Cite

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“…A [1] (c) (d) [4] for CGRAs deal only with the straight-line code sequence (basic block) of the innermost loop of a kernel. In case of conditional present in the innermost loop, the compilers use predication [45] techniques to convert the control flows into data flow structures. Indeed, these compilers can only generate code to execute a single loop, as a set of pipelined stages is repeatedly executed up to a certain number (loop boundary / number of pipelined stages) specified by the compiler.…”

Section: Introductionmentioning

confidence: 99%

“…On the other hand, large CGRA architectures for high performance computing have frequently resorted to predication techniques to expose parallelism across control dependencies, such as conditionals [45] [19]. Unfortunately, predication leads to waste of resources and it is hard to justify in an extremely power and area constrained scenario [55].…”

Section: Introductionmentioning

confidence: 99%

An Energy-Efficient Integrated Programmable Array Accelerator and Compilation Flow for Near-Sensor Ultralow Power Processing

Das

Martin

Rossi

et al. 2019

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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In this paper we give a fresh look to Coarse Grained Reconfigurable Arrays (CGRAs) as ultra-low power accelerators for near-sensor processing. We present a general-purpose Integrated Programmable-Array accelerator (IPA) exploiting a novel architecture, execution model, and compilation flow for application mapping that can handle kernels containing complex control flow, without the significant energy overhead incurred by state of the art predication approaches. To optimize the performance and energy efficiency, we explore the IPA architecture with special focus on shared memory access, with the help of the flexible compilation flow presented in this paper. We achieve a maximum energy gain of 2×, and performance gain of 1.33× and 1.8× compared with state of the art partial and full predication techniques, respectively. The proposed accelerator achieves an average energy efficiency of 1617 MOPS/mW operating at 100MHz, 0.6V in 28nm UTBB FD-SOI technology, over a wide range of near-sensor processing kernels, leading to an improvement up to 18×, with an average of 9.23× (as well as a speed-up up to 20.3×, with an average of 9.7×) compared to a core specialized for ultra-low power near-sensor processing.

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