Design for suppression of gate-induced drain leakage in LDD MOSFETs using a quasi-two-dimensional analytical model

Parke, S.; Moon, J.E.; Wann, H.-J.; Ko, P.K.; Hu, Chenming

doi:10.1109/16.141236

Cited by 96 publications

(36 citation statements)

References 16 publications

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“…Although it is enough to assume for a 1 m device, this assumption yields an peak which is too narrow for m. The GIDL model was also refined to better fit experimental data. The formula for is [5] (2) 0741-3106/98$10.00 © 1998 IEEE The drain enhancement parameter depends on the drain doping profile. Fig.…”

Section: Discussionmentioning

confidence: 99%

Simulation of SOI devices and circuits using BSIM3SOI

Sinitsky¹,

Tang

Jangity

et al. 1998

IEEE Electron Device Lett.

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A versatile SOI model derived from the BSIM3v3 bulk MOSFET model is capable of simulating partially and fully depleted devices with options for self-heating and floating body effects. The model can automatically switch between fully and partially depleted regimes. After refining body current models we for the first time present successful dc and transient device and circuit simulation of an SOI MOSFET technology with L L L e below 0.2 m.

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Section: Discussionmentioning

confidence: 99%

Simulation of SOI devices and circuits using BSIM3SOI

Sinitsky¹,

Tang

Jangity

et al. 1998

IEEE Electron Device Lett.

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“…To simplify the simulated structure, body and drain electrodes were placed at the back of the structure. The simulations were based on a two-dimensional (2-D) GIDL model [15], in which the band-to-band tunneling generation rate (G BBT ) of hole-electron pairs is a function of the total electric field (E TOT = (E . This generation mechanism is implemented into the right hand of the continuity equation [16].…”

Section: Asymmetric Gidlmentioning

confidence: 99%

Asymmetric gate-induced drain leakage and body leakage in vertical MOSFETs with reduced parasitic capacitance

Gili

Kunz

Uchino

et al. 2006

IEEE Trans. Electron Devices

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Abstract-Vertical MOSFETs, unlike conventional planar MOSFETs, do not have identical structures at the source and drain, but have very different gate overlaps and geometric configurations. This paper investigates the effect of the asymmetric source and drain geometries of surround-gate vertical MOSFETs on the drain leakage currents in the OFF-state region of operation. Measurements of gate-induced drain leakage (GIDL) and body leakage are carried out as a function of temperature for transistors connected in the drain-on-top and drain-on-bottom configurations. Asymmetric leakage currents are seen when the source and drain terminals are interchanged, with the GIDL being higher in the drain-on-bottom configuration and the body leakage being higher in the drain-on-top configuration. Band-to-band tunneling is identified as the dominant leakage mechanism for both the GIDL and body leakage from electrical measurements at temperatures ranging from −50 to 200• C. The asymmetric body leakage is explained by a difference in body doping concentration at the top and bottom drain-body junctions due to the use of a p-well ion implantation. The asymmetric GIDL is explained by the difference in gate oxide thickness on the vertical 110 pillar sidewalls and the horizontal 100 wafer surface.Index Terms-Band-to-band tunneling, body leakage, fillet local oxidation (FILOX), gate-induced drain leakage (GIDL), leakage current, vertical MOSFET.

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“…The edge charge trapping at the interface of this overlap region has a strong influence on the gate-induced drain leakage current resulting from the drain band-to-band tunneling because the band-toband tunneling current has an exponential dependence on the silicon surface electric field in the overlap region. [5][6][7][8] As a small change in the electric field due to the edge charge trapping could cause a significant change in the band-to-band tunneling leakage current, the edge charge trapping could be a reliability concern for MOS transistors and flash memory devices. Obviously, a study on the influence of the nitridation of the gate oxide on the edge charge trapping and thus on the band-to-band tunneling current is necessary.…”

Section: Influence Of Interfacial Nitrogen On Edge Charge Trapping Atmentioning

confidence: 99%

Influence of interfacial nitrogen on edge charge trapping at the interface of gate oxide/drain extension in metal–oxide–semiconductor transistors

Chen

Huang

Tse

et al. 2003

Applied Physics Letters

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Design for suppression of gate-induced drain leakage in LDD MOSFETs using a quasi-two-dimensional analytical model

Cited by 96 publications

References 16 publications

Simulation of SOI devices and circuits using BSIM3SOI

Simulation of SOI devices and circuits using BSIM3SOI

Asymmetric gate-induced drain leakage and body leakage in vertical MOSFETs with reduced parasitic capacitance

Influence of interfacial nitrogen on edge charge trapping at the interface of gate oxide/drain extension in metal–oxide–semiconductor transistors

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