Design of an ultralow power CNTFET based 9T SRAM with shared BL and half select free techniques

Patel, Pramod Kumar; Malik, М. M.; Gupta, Tarun Kumar

doi:10.1002/jnm.2511

Cited by 14 publications

(9 citation statements)

References 23 publications

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“…The authors' work in [7][8]is a comparative investigation of resistive bridging defects at nanoscale nodes of 90nm, 65nm, and 40nm. This investigation is carried out for a variety of resistive values, power supply voltage, memory size, and temperature.…”

Section: Related Workmentioning

confidence: 99%

Design and implementation of 10T-SRAM cell using Carbon Nano Tube Field Effect Transistor

Gujjula¹,

Kellampalli²

2023

IJSMEM

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SRAM is a key component in many VLSI circuits for efficient storage data. Various researches have been performed on implementation of SRAM using Conventional CMOS, FinFET and GNRFET technologies. But, these methodologies generating the more number of faults with high power and delay consumption, tosolve this problem proposed10T SRAM cell is implemented with the CNTFET respectively. Present research involving CNTFET SRAM deals with leakage analysis and dealt with the dual hilarity characteristics. Fault introduction and analysis of faults were limited with CMOS SRAM. The detection algorithms and circuits possess limitations in terms of detecting the current at nanoscales and restricted with CMOS SRAM. These limitations made us to pursue the research in these areas to bring novel ideas. The performance metrics evaluated and experimental analysis is made and it helps us to choose between various SRAMS. The simulation results shows that the proposed 10T SRAM consumes less delay and power compared to the 7T SRAM cell.

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Section: Related Workmentioning

confidence: 99%

Design and implementation of 10T-SRAM cell using Carbon Nano Tube Field Effect Transistor

Gujjula¹,

Kellampalli²

2023

IJSMEM

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“…Some of them exhibited comparative works to show the advantages of CNTFETs over CMOSs and FinFETs in bitcells due to extensive electrical properties of CNTs and excellent characteristics of CNTFETs [42–61]. They also reported that bitcells suffered from leakage power [10, 12, 36, 66, 67], Delay [36, 66–69], worse Read SNM [34, 49, 52, 66], negative impacts of nearthreshold supply voltage on delays and SNM [41, 68], subthreshold leakage currents [57], etc., and suggested different techniques, such as ‘decoupled R/W BLs’ [34–47, 66, 68] and ‘power‐gating’ [41, 42, 63–65], to solve those problems.…”

Section: Introductionmentioning

confidence: 99%

Challenges and solutions of working under threshold supply‐voltage, for CNTFET‐based SRAM‐bitcell

Shahrabadi

2022

IET Circuits, Devices & Syst

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Recently, several studies were done on SRAM bitcells at different supply‐voltages; upper, near or lower to threshold voltage. To the best of the author's knowledge, none of them discussed at threshold supply‐voltage with proper subthreshold operations and Nano/Pico power‐dissipations, hence this paper decides to investigate challenges and solutions of designing at VboldDboldD ${\mathbf{V}}_{\mathbf{D}\mathbf{D}}$ = Vboldtboldh ${\mathbf{V}}_{\mathbf{t}\mathbf{h}}$, because this voltage will lead to having lower power consumptions. This research applies power‐gating technique to adjust VboldDboldD ${\mathbf{V}}_{\mathbf{D}\mathbf{D}}$ on Vboldtboldh ${\mathbf{V}}_{\mathbf{t}\mathbf{h}}$, and also utilises output‐inverter to set Logic 1 at VboldDboldD ${\mathbf{V}}_{\mathbf{D}\mathbf{D}}$. Although ‘power‐gating’ and ‘output‐inverter’ were used in other works, this study renders specific points about them. In fact, the ability of power‐gating technique in adjusting VboldDboldD ${\mathbf{V}}_{\mathbf{D}\mathbf{D}}$ on Vboldtboldh ${\mathbf{V}}_{\mathbf{t}\mathbf{h}}$ without any instabilities in bitcell operation was not reported before, as well as, the idea of employing output‐inverter in read path for setting Logic‐1 at VboldDboldD ${\mathbf{V}}_{\mathbf{D}\mathbf{D}}$. It also proposed SNM% as a useful figure‐of‐merit. The goal of this study is not to present new circuits for bitcell, but is to investigate challenges and solutions of working under ‘VboldDboldD=Vboldtboldh ${\mathbf{V}}_{\mathbf{D}\mathbf{D}}={\mathbf{V}}_{\mathbf{t}\mathbf{h}}$’ which these solutions can lead to having an optimum bitcell.

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“…The CNTFETs are primarily alluring due to the plausibility of close ballistic channel transport, low leakage current, simple use of high‐k gate insulator, and advance device material science . The extraordinary electrical property of CNT provides the most appropriate and reliable option in contrast to cutting edge high‐speed nanoelectronics gadgets, which may be utilized like memory components . In general, the silicon based MOSFET cell is very much delicate to temperature variations when contrasted with the CNTFET based memory cell .…”

Section: Introductionmentioning

confidence: 99%

“…10 The extraordinary electrical property of CNT provides the most appropriate and reliable option in contrast to cutting edge high-speed nanoelectronics gadgets, which may be utilized like memory components. 11 In general, the silicon based MOSFET cell is very much delicate to temperature variations when contrasted with the CNTFET based memory cell. 12 SRAM memory cell has many applications in modern computer systems like cache memory of the computer, laptop, A to D converter, high-speed resistor, and electronics toys.…”

Section: Introductionmentioning

confidence: 99%

Design and analysis of CNTFET based 10T SRAM for high performance at nanoscale

Kumar

Ubhi

2019

Circuit Theory & Apps

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Summary The proposed 10T SRAM cell design is implemented for different CNTFET parameters like pitch, number of tubes, chirality, dielectric materials, and flatband voltage to analyze its effect on various performance parameters. The channel gate width, average read, and write power increase, but leakage power, read delay, and write delay decrease with the increase in pitch of CNTFET, whereas all these parameters are directly proportional to the number of tubes. Chirality alteration shows inverse effect on threshold voltage, read delay, and write delay although other parameters are directly related to it. The performance parameters are evaluated for various dielectric materials, and HfO2 gives the best results for low power and high‐speed applications. Analysis of flatband voltage on proposed 10T SRAM is performed by keeping flatband voltage constant for n‐CNTFET and varied for p‐CNTFET. Extensive analysis has been done to scrutinize the sharing of powers and delay of 10T SRAM because of variations in supply voltage and temperature. The supply voltage sweeps for a range between 0.6 and 1.2 V, and range of temperature variation is considered from −27 to 127°C. The stability of the proposed SRAM cell is calculated using N‐curve method to find voltage and current information. The CNTFET based 10T SRAM cell depicts that it persists supply voltage and temperature variation significantly superior than CMOS.

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Design of an ultralow power CNTFET based 9T SRAM with shared BL and half select free techniques

Cited by 14 publications

References 23 publications

Design and implementation of 10T-SRAM cell using Carbon Nano Tube Field Effect Transistor

Design and implementation of 10T-SRAM cell using Carbon Nano Tube Field Effect Transistor

Challenges and solutions of working under threshold supply‐voltage, for CNTFET‐based SRAM‐bitcell

Design and analysis of CNTFET based 10T SRAM for high performance at nanoscale

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