2020
DOI: 10.12737/2219-0767-2020-13-1-17-24
|View full text |Cite
|
Sign up to set email alerts
|

Design of Fault-Tolerant Chip Interfaces

Abstract: The article discusses the process of designing the interface of fault-tolerant chips. A redundant internal interface is designed for integrating system components on chips into a single information exchange system. The paper describes the interface for the four-channel construction of the VLSI chip of the BMC SNK. Special attention is paid to the description of interface signals.

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...

Citation Types

0
0
0

Year Published

2021
2021
2023
2023

Publication Types

Select...
5

Relationship

0
5

Authors

Journals

citations
Cited by 9 publications
references
References 4 publications
0
0
0
Order By: Relevance