Design of Ternary D-latch Using Graphene Nanoribbon Field Effect Transistor

Madhuri, Badugu Divya; Sunithamani, S.

doi:10.1109/vitecon.2019.8899731

Cited by 13 publications

(4 citation statements)

References 15 publications

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“…In the proposed designs, the Si is used as substrate where electron–electron interactions are strong. Hence, the high Fermi velocity is expected as 10 6 m/s (Nascimento et al , 2019; Divya and Sunithamani, 2019; Huei, 2014).…”

Section: Graphene Nanoribbon and Its Behaviourmentioning

confidence: 99%

Design of bilayer graphene nanoribbon tunnel field effect transistor

Vobulapuram¹,

Basha

Venkatramana³

et al. 2021

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Purpose The purpose of this paper is to design novel tunnel field effect transistor (TFET) using graphene nanoribbons (GNRs). Design/methodology/approach To design the proposed TFET, the bilayer GNRs (BLGNRs) have been used as the channel material. The BLGNR-TFET is designed in QuantumATK, depending on 2-D Poisson’s equation and non-equilibrium Green’s function (NEGF) formalism. Findings The performance of the proposed BLGNR-TFET is investigated in terms of current and voltage (I-V) characteristics and transconductance. Moreover, the proposed device performance is compared with the monolayer GNR-TFET (MLGNR-TFET). From the simulation results, it is investigated that the BLGNR-TFET shows high current and gain over the MLGNR-TFET. Originality/value This paper presents a new technique to design GNR-based TFET for future low power very large-scale integration (VLSI) devices.

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Section: Graphene Nanoribbon and Its Behaviourmentioning

confidence: 99%

Design of bilayer graphene nanoribbon tunnel field effect transistor

Vobulapuram¹,

Basha

Venkatramana³

et al. 2021

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show abstract

“…The value of E g can be calculated from the mathematical equation presented in Madhuri and Sunithamani. 25 The threshold voltage of GNRFETs for different values of GNR widths is plotted in Figure 1A. For the validation of the results, quantumwise ATK simulations are performed for all corresponding GNR width values.…”

Section: Introductionmentioning

confidence: 99%

“…The threshold voltage of GNRFET calculated as

V_{th} = \frac{Eg}{3 e},

where E g and e denote the GNR bandgap and electron charge. The value of E g can be calculated from the mathematical equation presented in Madhuri and Sunithamani 25 . The threshold voltage of GNRFETs for different values of GNR widths is plotted in Figure 1A.…”

Section: Introductionmentioning

confidence: 99%

Crosstalk reduction in copper on‐chip interconnects with graphene barrier for ternary logic applications

Madhuri

Sunithamani

2020

Circuit Theory & Apps

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This paper presents the investigations of crosstalk effects in ternary logic-based coupled interconnects. The crosstalk analysis is investigated for coupled copper interconnects and copper-multilayer graphene (Cu-MLG) interconnects. In Cu-MLG interconnects, the Cu interconnect is enclosed with MLG barrier and standard ternary inverter is used to drive the interconnect. Based on the industry standard HSPICE simulation results, the crosstalk effects such as noise peak and delay are lower compared with conventional Cu interconnects. Moreover, the Cu-MLG interconnects show reduced power dissipation, power delay product (PDP), and energy delay product (EDP) over the Cu interconnects. From the simulation results, it is observed that the Cu-MLG interconnects provides the performance improvements up to 30.67% compared with the Cu interconnects. Thus, the Cu-MLG interconnects are more compatible for ternary logic integrated circuits compared with traditional Cu interconnects.

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“…[19][20][21] However, limited studies have found on ternary GNRFETs and GNR interconnects. 15,[22][23][24] In the fabrication of VLSI circuits, transferring the power and ground to the field effect transistors is a challenging task. The high resistance in power interconnects reduces the performance and leads to logic failure of IC; whereas in the on-chip interconnects the high resistance leads to increase in propagation delay.…”

mentioning

confidence: 99%

Simultaneous Switching Noise Effects in Graphene-Based Power Distribution Networks

Vobulapuram¹

2023

ECS J. Solid State Sci. Technol.

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The simultaneous switching noise (SSN) effects in graphene nanoribbon field effect transistor (GNRFET) based ternary circuits are presented in this study. The performance in terms of SSN induced peak noise and propagation delay on power and ground rails are investigated in multilayer graphene nanoribbon (MLGNR) bundled power interconnects using Hewlett simulation program with integrated circuit emphasis (HSPICE) simulator. Furthermore, these investigations are compared to the copper (Cu) and multiwalled carbon nanotubes (MWCNT) based power interconnects. From the results, it is noticed that the proposed MLGNR interconnects shows performance improvements up to 74.9% and 33.8% over the Cu and MWCNT interconnects. Moreover, the SSN peak noise and delay are investigated for different interconnect lengths from 200 to 500 μm. It is observed that the SSN noise on power and ground rail is reduced and propagation delay is increased as interconnect length is increased.

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Design of Ternary D-latch Using Graphene Nanoribbon Field Effect Transistor

Cited by 13 publications

References 15 publications

Design of bilayer graphene nanoribbon tunnel field effect transistor

Design of bilayer graphene nanoribbon tunnel field effect transistor

Crosstalk reduction in copper on‐chip interconnects with graphene barrier for ternary logic applications

Simultaneous Switching Noise Effects in Graphene-Based Power Distribution Networks

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