Direct Measurement of SET Pulse Widths in 0.2-$\mu$m SOI Logic Cells Irradiated by Heavy Ions

Yanagawa, Yoshimitsu; Hirose, Kazuyuki; Saito, Hirobumi; Kobayashi, Daisuke; Fukuda, Seisuke; Ishii, Shigeru; Takahashi, Daisuke; Yamamoto, Kazuya; Kuroda, Yoshihiro

doi:10.1109/tns.2006.885110

Cited by 40 publications

(27 citation statements)

References 9 publications

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“…A scheme to verify the performance of the fabricated measurement circuit is necessary. From now, representative measurement circuits that have been proposed in [8][9][10] are examined from these five points.…”

Section: R5: Certainty Of Measured Widthmentioning

confidence: 99%

“…Pulse-triggered capturing circuit has been used in [8,9]. In this circuit, delayed SET pulse is captured in FFs, where the amount of delay is different for each FF.…”

Section: B Pulse-triggered Capturing Circuitmentioning

confidence: 99%

“…It adopts an exclusive-or gate and a delay element as depicted in Fig. 7 similarly to [9,10]. In this circuit, an input transition is converted into a pulse whose pulse width is equal to the propagation delay of the delay element.…”

Section: Assurance Of Pulse Width Using On-chip Pulse Generatormentioning

confidence: 99%

“…Meanwhile, several circuits have been proposed and successfully used for measuring the SET pulse width [8][9][10][11]. They directly measure the pulse width of each SET [8,9,11], or indirectly estimate the distribution of the SET pulse width from the statistic of SET errors [10].…”

Section: Introductionmentioning

confidence: 99%

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Measurement Circuits for Acquiring SET Pulse Width Distribution with Sub-FO1-Inverter-Delay Resolution

Harada

Mitsuyama

Hashimoto

et al. 2010

IEICE Trans. Fundamentals

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Abstract-This paper presents two circuits to measure pulse width distribution of single event transients (SETs). We first review requirements for SET measurement in accelerated neutron radiation test and point out problems of previous works, in terms of time resolution, time/area efficiency for obtaining large samples and certainty in absolute values of pulse width. We then devise two measurement circuits and a pulse generator circuit that satisfy all the requirements and attain sub-FO1-inverter-delay resolution, and propose a measurement procedure for assuring the absolute width values. The operation of one of the proposed circuits was confirmed by a preliminary radiation experiment of alpha particles with a fabricated test chip.

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Section: R5: Certainty Of Measured Widthmentioning

confidence: 99%

“…Pulse-triggered capturing circuit has been used in [8,9]. In this circuit, delayed SET pulse is captured in FFs, where the amount of delay is different for each FF.…”

Section: B Pulse-triggered Capturing Circuitmentioning

confidence: 99%

Section: Assurance Of Pulse Width Using On-chip Pulse Generatormentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Measurement Circuits for Acquiring SET Pulse Width Distribution with Sub-FO1-Inverter-Delay Resolution

Harada

Mitsuyama

Hashimoto

et al. 2010

IEICE Trans. Fundamentals

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show abstract

“…The SET characteristics (width, cross-section) are then measured with a detection circuit connected at the output of the target circuit. These detection circuits use, in some cases, a temporal delay based on a starved inverter [2,5,6] or, in other cases, latch cells connected at several nodes in an inverter chain [7,8,9,10,11]. The measurement resolution of the SET width by using these techniques is intrinsically limited to the inverter delay, and thus depends on the technology.…”

mentioning

confidence: 99%

A new technique for SET pulse width measurement in chains of inverters using pulsed laser irradiation

Ferlet-Cavrois¹,

McMorrow²,

Kobayashi³

et al. 2008

2008 European Conference on Radiation and Its Effects on Components and Systems

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An infrastructure for accurate characterization of single-event transients in digital circuits

Veeravalli

Polzer

Schmid

et al. 2013

Microprocessors and Microsystems

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We present the architecture and a detailed pre-fabrication analysis of a digital measurement ASIC facilitating long-term irradiation experiments of basic asynchronous circuits, which also demonstrates the suitability of the general approach for obtaining accurate radiation failure models developed in our FATAL project. Our ASIC design combines radiation targets like Muller C-elements and elastic pipelines as well as standard combinational gates and flip-flops with an elaborate on-chip measurement infrastructure. Major architectural challenges result from the fact that the latter must operate reliably under the same radiation conditions the target circuits are exposed to, without wasting precious die area for a rad-hard design. A measurement architecture based on multiple non-rad-hard counters is used, which we show to be resilient against double faults, as well as many triple and even higher-multiplicity faults. The design evaluation is done by means of comprehensive fault injection experiments, which are based on detailed Spice models of the target circuits in conjunction with a standard double-exponential current injection model for single-event transients (SET). To be as accurate as possible, the parameters of this current model have been aligned with results obtained from 3D device simulation models, which have in turn been validated and calibrated using micro-beam radiation experiments at the GSI in Darmstadt, Germany. For the latter, target circuits instrumented with high-speed sense amplifiers have been used for analog SET recording. Together with a probabilistic analysis of the sustainable particle flow rates, based on a detailed area analysis and experimental cross-section data, we can conclude that the proposed architecture will indeed sustain significant target hit rates, without exceeding the resilience bound of the measurement infrastructure.

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Direct Measurement of SET Pulse Widths in 0.2-$\mu$m SOI Logic Cells Irradiated by Heavy Ions

Cited by 40 publications

References 9 publications

Measurement Circuits for Acquiring SET Pulse Width Distribution with Sub-FO1-Inverter-Delay Resolution

Measurement Circuits for Acquiring SET Pulse Width Distribution with Sub-FO1-Inverter-Delay Resolution

A new technique for SET pulse width measurement in chains of inverters using pulsed laser irradiation

An infrastructure for accurate characterization of single-event transients in digital circuits

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