Direct Measurement of Top and Sidewall Interface Trap Density in SOI FinFETs

Kapila, G.; Kaczer, B.; Nackaerts, A.; Collaert, N.; Groeseneken, G.

doi:10.1109/led.2007.891263

Cited by 98 publications

(73 citation statements)

References 8 publications

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“…The D it values compare quite well with the experimental D it values presented in Ref. [15] and also shown in Table II. As expected the D it value for FinFET E (with [110] channel and (110) sidewalls) is higher than FinFET B ([100] channel with (100) sidewalls).…”

Section: Dit Using S: Methods Isupporting

confidence: 87%

“…In the results section it will be further shown that also the theoretical E b value can over estimate the experimental E b value. These mismatches can be attributed to the presence of traps at the oxide-channel interface of multi-gate FETs where these traps can enhance the Electrostatic-static screening and suppress the action of the gate on the channel [6,7,15,16]. This simple idea is a powerful tool used for the estimation of interface trap density (D it ) in these undoped Si n-FinFETs.…”

Section: Trap Extraction Methodsmentioning

confidence: 99%

“…The interface trap charges are assumed to be situated very close to the oxide-channel interface for Eq.5 to be true. Also the interface trap density is assumed to be constant and identical for the top and the side walls of the FinFET which is generally not the case [15,16]. This method of extraction works best for undoped channel since any filling of the impurity/dopant states is neglected in the calculation.…”

Section: Trap Extraction Methodsmentioning

confidence: 99%

“…The reason for the first point is suggested to be the presence of interface traps in the FinFETs which screen the gate from the channel [6,7]. The second observation can be understood by the fact that [110] channels with (110) sidewalls have higher interface trap density due to the higher surface bond density [19] and poor anisotropic etching of the (110) sidewalls [15,16].…”

Section: Evolution Of E B and S With Vgsmentioning

confidence: 99%

“…However, the theoretically obtained S and E b values quantitatively over-estimated the experimental values. The reduced experimental values can be attributed to the presence of interface traps in these FinFETs [5,6,15,16]. The effect of interface traps on channel property are even more dominant in the extremely thin FinFETs [7].…”

Section: Introductionmentioning

confidence: 99%

See 4 more Smart Citations

Interface trap density metrology from sub-threshold transport in highly scaled undoped Si n-FinFETs

Paul

Tettamanzi

Lee

et al. 2011

Journal of Applied Physics

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Channel conductance measurements can be used as a tool to study thermally activated electron transport in the sub-threshold region of state-of-art FinFETs. Together with theoretical TightBinding (TB) calculations, this technique can be used to understand the evolution of source-tochannel barrier height (E b ) and of active channel area (S) with gate bias (Vgs). The quantitative difference between experimental and theoretical values that we observe can be attributed to the interface traps present in these FinFETs. Therefore, based on the difference between measured and calculated values of (i) S and (ii) |∂E b /∂Vgs| (channel to gate coupling), two new methods of interface trap density (Dit) metrology are outlined. These two methods are shown to be very consistent and reliable, thereby opening new ways of analyzing in situ state-of-the-art multi-gate FETs down to the few nm width limit. Furthermore, theoretical investigation of the spatial current density reveal volume inversion in thinner FinFETs near the threshold voltage.

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Section: Dit Using S: Methods Isupporting

confidence: 87%

Section: Trap Extraction Methodsmentioning

confidence: 99%

Section: Trap Extraction Methodsmentioning

confidence: 99%