Domain Magnet Logic (DML): A new approach to magnetic circuits

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

et al. 2017

In the post-CMOS scenario, Field Coupled Nanotechnologies represent an innovative and interesting new direction for electronic nanocomputing. Among these technologies, NanoMagnet Logic (NML) makes it possible to finally embed logic and memory in the same device. To fully analyze the potential of NML circuits, design tools that mimic the CMOS design-flow should be used for circuit design.We present, in this manuscript, the latest and improved version of ToPoliNano, our design and simulation framework for Field Coupled Nanotechnologies. ToPoliNano emulates the top-down design process of CMOS technology. Circuits are described with a VHDL netlist and layout is then automatically generated considering in-plane NML (iNML) technology. The resulting circuits can be simulated and performance can be analyzed. In this work, we describe several enhancements to the tool itself, like a circuit editor for custom design of Field Coupled Nanodevices, improved algorithms for netlist optimization and new algorithms for the place and route of iNML circuits. We have validated and analyzed the tool by using extensive metrics, both by using standard circuits and ISCAS 85 benchmarks. This contribution highlights the improvements of ToPoliNano, which is now a innovative and complete tool for the development of iNML technology.

Section: A Overview On Existing Toolsmentioning

confidence: 82%

“…Indeed, with this limitation vertical connections assume a stair-like behavior [30]. However, as demonstrated in [31], the use of domain walls for vertical interconnection can solve the problem. The domain wall is a long magnet with a minimum height of around 300nm.…”

Section: A Overview On Existing Toolsmentioning

confidence: 99%

ToPoliNano: A CAD Tool for Nano Magnetic Logic

Riente

Turvani

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

et al. 2017

“…MTJ can be integrated to use as input and output interfaces [31]. In [15] domain walls are embedded into the circuit developing a new logic solution, called Domain Magnet Logic (DML), that reduces the overhead caused by the interconnections. An important feature of NML technology is that power consumption depends on circuits area.…”

Section: The Clock Systemmentioning

confidence: 99%

“…This is the main point that we address in our work: studying a clock system that enables the reduction of circuits area can ultimately lead to low power circuits, even if the power necessary for the RESET state generation is higher (see Section II). Another point suggests to further investigate the technique based on magnetic field generation: the magnetic field clock enables the integration of other magnetic structures inside NML circuits, like domain walls [15], leading to further advantages in terms of area reduction, while other clocking techniques might not.…”

Section: Introductionmentioning

confidence: 99%

Virtual Clocking for NanoMagnet Logic

IEEE Trans. Nanotechnology

Cairo

Turvani

et al. 2016

Among emerging technologies NanoMagnet Logic (NML) has recently received particular attention. NML uses magnets as constitutive elements, and this leads to logic circuits where there is no need of an external power supply to maintain their logic state. As a consequence, a system with intrinsic memory and zero stand-by power consumption can be envisioned. Despite the interesting nature of NML, a fundamental open problem still calls for a solution that could really boost NML technology: the clock system. It constrains the layout of circuits and leads to a potentially high dynamic power consumption if not carefully conceived. The first clock system developed was based on the generation of a magnetic field through an on-chip current. After that other types of NML, based on several different types of clock systems, were proposed to improve clocking.We present here our proposal for a new clock delivery method. We named this system "Virtual Clock". It offers several important advantages over previous solutions. First, it notably simplifies the clock generation network, reducing the complexity of the fabrication process. It improves the efficiency of circuits layout, substantially reducing interconnections overhead and boosting the reliability of the majority voter. It enables the fabrication of in-plane NML circuits with two layers, while they were confined to one single layer up to now. Finally, it allows to globally reduce dynamic power consumption by considerably shrinking circuits area. Overall the "Virtual Clock" system we propose represents an important step forward in the development of NML technology.

“…It enables to safely use the majority voter, the basic logic gate of this technology, also considering the constraints related to the fabrication of clock wire (more details are in Section IV). It allows us to build magnetic interconnections in NML circuits using domain walls, as we demonstrated in [14], greatly reducing interconnections overhead. Finally, placing clock wires above and under the magnets, as suggested in [3], it is possible to build multilayer NML circuits.…”

Section: Background On Nmlmentioning

confidence: 99%

Logic-in-Memory: A Nano Magnet Logic Implementation

Cofano

Santoro

2015 IEEE Computer Society Annual Symposium on VLSI

et al. 2015

Self Cite

In most computational systems memory access represents a relevant bottleneck for circuits performance. The execution speed of algorithms is severely limited by memory access time. An emerging technology like NanoMagnet Logic (NML), where its magnetic nature leads to an intrinsic memory ability, represents therefore a very promising opportunity to solve this issue. NanoMagnet Logic is the ideal candidate to implement the so called Logic-In-Memory (LIM) architecture. But how is it possible to organize an architecture where logic and memory are mixed and not separated entities?In this paper we try to address this issue presenting our recent developments on LIM architectures. We originally conceived a LIM architecture without considering any technological constraints. Here we present the first adaptation of that architecture to NanoMagnet Logic technology. The architecture is based on an array of identical cells developed on three virtual layers, one for logic, one for memory and one for information routing. These three virtual layers are mapped on two physical layers exploiting all our recent improvements on NanoMagnet Logic technology, which are validated with the help of low level simulations. The structure has been tested implementing two different algorithms, a sort algorithm and an image manipulation algorithm. A complete characterization in terms of area and power is reported. The structure here presented is therefore the first step of an ongoing effort directed toward the development of truly innovative architectures.