Double dielectrics enhancement on the LDMOS using high-k field dielectric and low-k buried dielectric

Yao, Jiafei; Liu, Xin; Sun, Mingshun; Xu, Tianci; Li, Man; Chen, Jing; Zhang, Maolin; Zhang, Jun; Guo, Yufeng

doi:10.1016/j.rinp.2022.105599

Cited by 5 publications

(5 citation statements)

References 19 publications

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“…The higher permittivity could optimize the potential and electric field distribution to improve the BV and increase the drift doping concentration to reduce R on,sp . However, the BV is decreased when continuing to increase ε fin because of the rapid breakdown near the drain [10]. Therefore, there is an optimized FOM for the HKMF-LDMOS with different n i 's.…”

Section: Resultsmentioning

confidence: 99%

“…In order to obtain the high breakdown characteristics and reduce the specific ON-resistance, high-k dielectric is employed in the SOI LDMOS. One method is depositing the high-k film on the surface of the top silicon layer, which modulates the lateral electric field distribution, but has little effect on the vertical electric field and weak assisted depletion effect on the drift region [8], [9], [10]. Another method is depositing the high-k dielectric into the deep trench with the integration of variable-k technology, trench gate technology, and so on; the figure of merit (FOM) of the SOI LDMOS is significantly improved, but the fabrication process is more complex [11], [12], [13].…”

Section: Introductionmentioning

confidence: 99%

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SOI LDMOS With High-k Multi-Fingers to Modulate the Electric Field Distributions

Yao

Sun

et al. 2023

IEEE Trans. Electron Devices

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The silicon-on-insulator (SOI) lateral doublediffused metal-oxide-semiconductor (LDMOS) with high-k multi-fingers (HKMFs) is proposed and investigated. The fingertips are distributed at specific locations to modulate the electric field distributions and improve the device performances. First, the electric field peaks formed at the fingertips could optimize the electric field distributions, which improves the breakdown voltage (BV) of the LDMOS effectively. Meanwhile, the multi-fingers are embedded into the drift region to increase the optimal drift doping concentration, which facilitates the positive conduction of the device and reduces the specific ON-resistance (R on,sp ). The simulation results show that the proposed HKMF-LDMOS with five multi-fingers increases the BV by 59.2%, reduces R on,sp by 37.8%, and improves the figure of merit (FOM) by 4.07 times when compared to the conventional LDMOS.

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Section: Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

SOI LDMOS With High-k Multi-Fingers to Modulate the Electric Field Distributions

Yao

Sun

et al. 2023

IEEE Trans. Electron Devices

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“…The introduction of Low-k (LK) dielectric material is intended to increase the vertical BV of the device through the application of enhanced dielectric layer field technology. Therefore, scholars have done a lot of research in this direction in recent years [9][10][11][12][13][14]. Cheng et al [9] introduced a HK thin film around the trench, the BV and R on,sp of LDMOS were effectively improved.…”

Section: Introductionmentioning

confidence: 99%

“…Moreover [10], proposed a LDMOS with HK multi-fingers, and the doping concentration is increased due to the drift region of HK dielectric. Yao et al [14] investigated a double dielectrics enhancement LDMOS with a HK field dielectric and a LK buried layer dielectric. The HK layer assists depletion while the LK buried layer sustains a high voltage to further optimize the performance of the LDMOS.…”

Section: Introductionmentioning

confidence: 99%

A novel double-gate trench SOI LDMOS with double-dielectric material by TCAD simulation study

Guo,

Dai,

Wang

et al. 2024

Semicond. Sci. Technol.

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In this paper, a novel double-gate trench silicon-on-insulator (SOI) lateral double-diffused metal oxide semiconductor field-effect transistor (LDMOS) with double-dielectric material (DGDK-LDMOS) is proposed. DGDK-LDMOS has two dielectric materials: a reverse-L-shaped high-k (HK) thin film and an low-k (LK) buried oxide layer. The HK thin film optimizes the electric field distribution on the drift region surface, attracting electric flux, and the excellent withstand voltage of the LK buried oxide layer can significantly improve the breakdown voltage (BV) and reduce specific on-resistance (Ron,sp) of the device. The modulation mechanism of LDMOS by HK thin film and LK buried oxide layer is analyzed. The results show that compared with conventional LDMOS (C-LDMOS), when the permittivity of HK thin film is 25 and the permittivity of LK buried oxide is 3, the BV of DGDK-LDMOS is increased by 89.6%, the Ron,sp is decreased by 26.4%, and the figure of merit (FOM, FOM = BV2/Ron,sp) is increased by 397.2% from 3.6 MW·cm−2 to 17.9 MW·cm−2. Meanwhile, the output characteristics, transfer characteristics, lattice temperature, AC characteristics and switching characteristics of DGDK-LDMOS are also discussed and compared.

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“…With the rapid development of power integrated circuits, traditional MOSFETs are no longer able to meet the demands. Since Y Tarui et al proposed LDMOS in 1971, scholars have studied and innovated the structure in order to adapt to high voltage integrated circuits [1][2][3]. LDMOS has been widely used due to its outstanding advantages such as thermal stability, frequency stability, high voltage tolerance and good compatibility with CMOS technology [4][5][6].…”

Section: Introductionmentioning

confidence: 99%

Study of ultra-low specific on-resistance and high breakdown voltage SOI LDMOS based on electron accumulation effect

Lyu,

Dai,

Wang

et al. 2023

Eng. Res. Express

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A novel stepped L-shaped trench gate silicon-on-insulator (SOI) lateral double-diffused metal oxide semiconductor field-effect transistor (LDMOS) with N-pillar (SLTGN-LDMOS) is proposed. SLTGN-LDMOS contains a highly doped N-pillar, assisting in reducing the specific on-resistance (Ron,sp). The stepped L-shaped trench gate (SLTG) attracts electrons to attach to the edge of the trench, thus directing more current to flow along the edge, which decreases Ron,sp effectively. Furthermore, new electric field peaks are generated on the surface of the drift region, thus increasing the breakdown voltage (BV). As a result, compared with the conventional structure (C-LDMOS), the BV of SLTGN-LDMOS increases from 63 V to 162.7 V, and the Ron,sp decreases from 1.85 mΩ·cm2 to 1.46 mΩ·cm2. Then, the figure of merit (FOM1, BV2 / Ron.sp) increases remarkably from 2.15 MW/cm2 to 18.13 MW/cm2. In addition, the maximum surface temperature of SLTGN-LDMOS is 395.3 K, slightly lower than the 398.7 K of C-LDMOS.

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Double dielectrics enhancement on the LDMOS using high-k field dielectric and low-k buried dielectric

Cited by 5 publications

References 19 publications

SOI LDMOS With High-k Multi-Fingers to Modulate the Electric Field Distributions

SOI LDMOS With High-k Multi-Fingers to Modulate the Electric Field Distributions

A novel double-gate trench SOI LDMOS with double-dielectric material by TCAD simulation study

Study of ultra-low specific on-resistance and high breakdown voltage SOI LDMOS based on electron accumulation effect

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