Dual-Edge Triggered T Flip-Flop Structure Using Quantum-Dot Cellular Automata

Xiao, Lin Rong; Xu, Xiang; Ying, Shi Yan

doi:10.4028/www.scientific.net/amr.662.562

Cited by 10 publications

(3 citation statements)

References 18 publications

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“…The proposed LST-FFs require three fixed inputs, and the proposed NET-FFs require four fixed inputs. Xiao et al [35] implemented a dual-edge triggered T flip-flop. Compared with [35], the proposed NET-FFs have a smaller cell count, smaller area, lower latency, and lower power consumption.…”

Section: Previous Clock Current Clock Outputmentioning

confidence: 99%

“…Xiao et al [35] implemented a dual-edge triggered T flip-flop. Compared with [35], the proposed NET-FFs have a smaller cell count, smaller area, lower latency, and lower power consumption. The area of the proposed NET-FF1 is smaller than that of the Table 5 shows the comparisons of the performance and energy consumption of the existing designs of LST-FFs and NET-FFs.…”

Section: Previous Clock Current Clock Outputmentioning

confidence: 99%

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Designs of Level-Sensitive T Flip-Flops and Polar Encoders Based on Two XOR/XNOR Gates

et al. 2022

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Quantum-dot cellular automata is a novel nanotechnology that has the advantages of low energy dissipation, easy integration, and high computing speed. It is regarded as one of the powerful alternative technologies for the next generation of integrated circuits because of its unique implementation concept. In this paper, two XOR/XNOR gates are proposed. Level-sensitive T flip-flops, negative edge-trigger T flip-flops, two-to-one multiplexers, reversible gates, and (8, 4) polar encoders are implemented based on these two proposed logic gates. Simulation results show that, compared with the existing level-sensitive T flip-flops, the second proposed level-sensitive T flip-flop has fewer cells and lower energy dissipation; compared with the best (8, 4) polar encoder, the cell count and area of the second proposed (8, 4) polar encoder are decreased by 13.67% and 12.05%, respectively. The two XOR/XNOR gates have a stable output and low energy dissipation, which can be flexibly designed into complex quantum-dot cellular automata circuits.

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Section: Previous Clock Current Clock Outputmentioning

confidence: 99%

Section: Previous Clock Current Clock Outputmentioning

confidence: 99%

Designs of Level-Sensitive T Flip-Flops and Polar Encoders Based on Two XOR/XNOR Gates

et al. 2022

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“…Cell counts Area (µm 2 ) Latency [24] 184 0.32 3 [25] 108 0.20 1.5 [21] 92 0.10 1.25 [26] 81 0.07 1.5 [22] 66 0.06 1.25 [27] 55 0.06 1.5 [10] 46 0.06 1 Proposed 21 0.0186 0.5…”

Section: Designmentioning

confidence: 99%

Synchronous Counter Design Using Novel Level Sensitive T-FF in QCA Technology

Majeed

Alkaldy

Zainal

et al. 2019

JLPEA

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The quantum-dot cellular automata (QCA) nano-technique has attracted computer scientists due to its noticeable features such as low power consumption and small size. Many papers have been published in the literature about the utilization of this technology for de-signing many QCA circuits and for presenting logic gates in an optimal structure. The T flip-flop, which is an essential part of digital designs, can be used to design synchronous and asynchronous counters. This paper presents a novel T flip-flop structure in an optimal form. The presented novel gate was used to design an N-bit binary synchronous counter. The QCADesigner software was used to verify the designed circuits and to present the simulation results, while the QCAPro tool was used for the power analysis. The proposed design required minimal power and showed good improvements over previous designs.

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