Dynamically Reconfigurable Dataflow Architecture for High-Performance Digital Signal Processing on Multi-FPGA Platforms

Voigt, Sven-Ole; Teufel, Thomas

doi:10.1109/fpl.2007.4380734

Search citation statements

Order By: Relevance

Paper Sections

Select...

Introduction1

Citation Types

Supporting

Mentioning

Contrasting

Year Published

2008

2020

Publication Types

Select...

Other2

Article1

Relationship

Self Cite1

Independent2

Authors

Journals

Cited by 3 publications

(1 citation statement)

References 4 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…In [1] we introduced a dynamically reconfigurable dataflow architecture that is composed of a variable topology [2]. The idea is based on reconfiguration.…”

Section: Introductionmentioning

confidence: 99%

Analysis of a Dynamically Reconfigurable Dataflow Architecture and its Scalable Parallel Extension for Multi-FPGA Platforms

Voigt

Teufel

2008

2008 16th International Symposium on Field-Programmable Custom Computing Machines

Self Cite

View full text Add to dashboard Cite

In this paper we analyze a dataflow architecture that maps efficiently onto modern FPGA architectures and is composed of communication channels which can be dynamically adapted to the algorithm's dataflow. The reconfiguration of the architecture's topology can be achieved within a single clock cycle while DSP operations are in progress. In order to maximize the bandwidth, the dataflow channel width is userdefinable and can be chosen based on the applicationspecific requirements. Furthermore, the dataflow architecture can be efficiently mapped onto multi-FPGA platforms increasing at the same time the overall communication bandwidth.

show abstract

“…In [1] we introduced a dynamically reconfigurable dataflow architecture that is composed of a variable topology [2]. The idea is based on reconfiguration.…”

Section: Introductionmentioning

confidence: 99%