Efficient interpolation and factorization in algebraic soft-decision decoding of reed-solonion codes

Koetter, R.; Ma, Jun; Vardy, Alexander; Ahmed, A.

doi:10.1109/isit.2003.1228381

Cited by 31 publications

(18 citation statements)

References 7 publications

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“…Re-encoding can be applied to reduce the interpolation complexity [5]- [7]. The purpose of re-encoding is to transform the coordinate of the interpolation points with highest multiplicities into zero, such that the interpolation on these points can be presolved by simple univariate interpolation.…”

Section: Soft-decision Rs Decoding Algorithmmentioning

confidence: 99%

“…Applying re-encoding, the number of iterations in the interpolation step can be reduced from around 14 000 in the previous example to around 700. Further complexity reduction of the interpolation algorithm can be achieved by coordinate transformation [5]- [7]. Applying coordinate transformation, some needlessly carried-around factors can be factored out of the interpolation process, which in turn reduces the memory requirements for storing the coefficients.…”

Section: Soft-decision Rs Decoding Algorithmmentioning

confidence: 99%

“…A degree two polynomial can be expressed as (7) where and . In the case , (7) can be reduced to (8) This equation can be solved by a cyclical shift using normal basis representation for Galois Field elements.…”

Section: Lemmamentioning

confidence: 99%

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Fast factorization architecture in soft-decision Reed-Solomon decoding

Zhang

Parhi

2005

IEEE Trans. VLSI Syst.

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Reed-Solomon (RS) codes are among the most widely utilized block error-correcting codes in modern communication and computer systems. Compared to its hard-decision counterpart, soft-decision decoding offers considerably higher error-correcting capability. The recent development of soft-decision RS decoding algorithms makes their hardware implementations feasible. Among these algorithms, the Koetter-Vardy (KV) algorithm can achieve substantial coding gain for high-rate RS codes, while maintaining a polynomial complexity with respect to the code length. In the KV algorithm, the factorization step can consume a major part of the decoding latency. A novel architecture based on root-order prediction is proposed in this paper to speed up the factorization step. As a result, the time-consuming exhaustive-search-based root computation in each iteration level, except the first one, of the factorization step is circumvented with more than 99% probability. Using the proposed architecture, a speedup of 141% can be achieved over prior efforts for a (255, 239) RS code, while the area consumption is reduced to 31.4%.

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Section: Soft-decision Rs Decoding Algorithmmentioning

confidence: 99%

Section: Soft-decision Rs Decoding Algorithmmentioning

confidence: 99%

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Fast factorization architecture in soft-decision Reed-Solomon decoding

Zhang

Parhi

2005

IEEE Trans. VLSI Syst.

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“…Interpolation은 매우 많은 반복 계산 과정을 포함하고 있어 레이턴시가 매우 큰데, 리인코딩(re-encoding) 기 법을 사용하여 반복 계산과정을 알고리즘 차원에서 줄 일 수 있다 [9] . 리인코딩은 확률이 높은 Interpolation 포 .…”

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Area-efficient Interpolation Architecture for Soft-Decision List Decoding of Reed-Solomon Codes

Lee¹,

Park²

2013

Journal of the Institute of Electronics Engineers of Korea

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Reed-Solomon (RS) codes are powerful error-correcting codes used in diverse applications. Recently, algebraic soft-decision decoding algorithm for RS codes that can correct the errors beyond the error correcting bound has been proposed. The algorithm requires very intensive computations for interpolation, therefore an efficient VLSI architecture, which is realizable in hardware with a moderate hardware complexity, is mandatory for various applications. In this paper, we propose an efficient architecture with low hardware complexity for interpolation in soft-decision list decoding of Reed-Solomon codes. The proposed architecture processes the candidate polynomial in such a way that the terms of X degrees are processed in serial and the terms of Y degrees are processed in parallel. The processing order of candidate polynomials adaptively changes to increase the efficiency of memory access for coefficients; this minimizes the internal registers and the number of memory accesses and simplifies the memory structure by combining and storing data in memory. Also, the proposed architecture shows high hardware efficiency, since each module is balanced in terms of latency and the modules are maximally overlapped in schedule. The proposed interpolation architecture for the (255, 239) RS list decoder is designed and synthesized using the DongbuHitek 0.18 standard cell library, the number of gate counts is 25.1K and the maximum operating frequency is 200 MHz.

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“…In this paper, we focus on a simplified version of the algorithm based on the reencoding and coordinate basis transformations [3,8,10,11] that reduce the number of iterations and memory requirements to practical levels. The resulting simplified soft-decision interpolation algorithm is run on O(n − k) interpolation points instead of O(n).…”

Section: B Reduced-complexity Decodingmentioning

confidence: 99%

SIMD implementation of interpolation in algebraic soft-decision Reed-Solomon decoding

Boulianne

Gross

IEEE Workshop on Signal Processing Systems Design and Implementation, 2005.

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Abstract-The Koetter-Vardy algorithm is an algebraic softdecision decoding algorithm for Reed-Solomon codes. Software implementations of the Koetter-Vardy algorithm are considered as part of a redecoding architecture that augments a hardware hard-decision decoder with soft-decision decoding software on an embedded processor. In this paper we investigate the implementation of the interpolation step of the Koetter-Vardy algorithm on SIMD processor architectures. A parallelization of the algorithm is given using the K'th order Horner's rule for parallel polynomial evaluation. The SIMD algorithm has a running time 2.5 to 4 times faster than a serial implementation on a DSP processor. To gain further speedup we propose a merged-SIMD architecture that calculates the Hasse derivative in parallel with the polynomial updates.

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Efficient interpolation and factorization in algebraic soft-decision decoding of reed-solonion codes

Cited by 31 publications

References 7 publications

Fast factorization architecture in soft-decision Reed-Solomon decoding

Fast factorization architecture in soft-decision Reed-Solomon decoding

Area-efficient Interpolation Architecture for Soft-Decision List Decoding of Reed-Solomon Codes

SIMD implementation of interpolation in algebraic soft-decision Reed-Solomon decoding

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