Electromigration-aware physical design of integrated circuits

Lienig, Jens; Jerke, Goeran

doi:10.1109/icvd.2005.88

Cited by 36 publications

(19 citation statements)

References 25 publications

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“…First of all, TSV's EM in 3D-IC is physically different from EM in planar IC. The strong influence of mechanical stress on TSV's EM makes the conventional EM-driven wire sizing or routing in planar IC [11] less useful in 3D-IC. In addition, redundant design which addresses EM issues in planer ICs by enabling reconfiguration of interconnects [10] is not quite applicable in 3D-IC due to TSV's high manufacturing cost, low yield, and relatively large dimension.…”

Section: Introductionmentioning

confidence: 99%

Electromigration-aware placement for 3D-ICs

Yang

Srivastava

2016

2016 17th International Symposium on Quality Electronic Design (ISQED)

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This paper presents a novel technique and algorithm for chip-scale electromigration (EM) aware 3D placement. A simple TSV's EM objective function is used, providing a computationally efficient way to represent TSV EM other than the finite-element-method (FEM) based simulation. Considering TSV's EM is mutually influenced by neighboring TSVs (due to TSV EM's dependence on TSV-induced thermal mechanical stress) and strongly affected by temperature, iterative optimizations are performed to obtain the optimal TSV's distribution and a desired TSV's temperature. Finally using a compact thermal model and simulated annealing, all logic gates are placed such that the desired temperature profile is reached. Results show that compared with a conventional wirelength centered 3D placer, our design achieves 3.41x longer mean-time-to-failure (MTTF), with only 3% wirelength overhead.

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Section: Introductionmentioning

confidence: 99%

Electromigration-aware placement for 3D-ICs

Yang

Srivastava

2016

2016 17th International Symposium on Quality Electronic Design (ISQED)

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“…Every technology's design rule manual (DRM) provides specific guidelines for the maximum current densities allowed to be used for each metal level to guarantee the promised metal lifetime at each level. So EM puts restrictions on the back-end physical design that the IC designer has to be aware of [7] and [8].…”

Section: Introductionmentioning

confidence: 99%

Effects of metal thickness variations on IC metal lifetime due to electromigration

Keshavarz

Dion

2009

2009 IEEE International Integrated Reliability Workshop Final Report

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In this paper the effect of Al-metal-thickness variations on the IC metal lifetime is investigated. Because the flow of currents in IC metals is mainly dictated by the front-end circuitry, metal thickness variations result in current-density changes in the IC metals. The change of current density, in turn, results in metal lifetime variations caused by Electromigration (EM). This effect is investigated and modeled in this work. Experimental data from eight month's of EM tests performed as part of the wafer-level reliability (WLR) tests on the BCD technology in STMicroelectronics were used as the basis for the approach. Accurate metal thickness at each measured site was extracted and used in lifetime extractions. Summarized results show that a 22% metal thickness reduction is sufficient to reduce the metal lifetime below 10 years.

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“…For more than 10 years, several authors have predicted new or enhanced fault mechanisms in CMOS logic based on nanostructures such as single and multiple event upsets [1,2], metal migration [3,4], hot carrier injection [5], negative bias thermal instabilities (NBTI) [6], and oxide breakdowns [7]. One reason is the on-going down-scaling of critical dimensions such as transistor channel length, while the level of supply and signal voltages has been more or less constant over several generations of IC technology.…”

Section: Introductionmentioning

confidence: 99%

Combining fault tolerance and self repair at minimum cost in power and hardware

Koal

Scholzel

Vierhaus

2014

17th International Symposium on Design and Diagnostics of Electronic Circuits &Amp; Systems

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Large-scale integrated circuits and systems fabricated in nano-technologies exhibit new and enhanced fault properties which limit both their reliability and their life time. Transient fault effects have found most attention so far. They must be handled by on-line check and fault compensation based on duplication and triplication, typically at a significant amount of extra power. Such techniques are not suitable for life time extension, since their redundant elements all undergo wear-out effects in hot operation. Repair technologies that perform a process of system re-organization and introduction of cold redundancy may extend system life time, but they are too slow to catch and correct transient and permanent fault effects in hot operation. The essential task therefore remains to find methods and architectures that will provide on-line check in combination with self repair techniques at a minimum cost in extra power.

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Electromigration-aware physical design of integrated circuits

Cited by 36 publications

References 25 publications

Electromigration-aware placement for 3D-ICs

Electromigration-aware placement for 3D-ICs

Effects of metal thickness variations on IC metal lifetime due to electromigration

Combining fault tolerance and self repair at minimum cost in power and hardware

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