Embedded DRAM: more than just a memory

Non-volatile memories are gaining significant attention for embedded cache application due to their low standby power and excellent retention. Domain wall memory (DWM) is one possible candidate due to its ability to store multiple bits per cell in order to break the density barrier. Additionally, it provides low standby power, fast access time, good endurance and retention. However, it suffers from poor write latency, shift latency, shift power and write power. DWM is sequential in nature and latency of read/write operations depends on the offset of the bit from the read/write head. This paper investigates the circuit design challenges such as bitcell layout, head positioning, utilization factor of the nanowire, shift power, shift latency and provides solutions to deal with these issues. A synergistic system is proposed by combining circuit techniques such as merged read/write heads (for compact layout), flipped-bitcell and shift gating (for shift power optimization), wordline (WL) strapping (for access latency), shift circuit design with micro-architectural techniques such as segmented cache to realize energy-efficient and robust DWM cache. Simulations show 3-33% better performance and 1.25X-14.4X better power over a wide range of PARSEC benchmarks.

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“…Fig. 14 shows that the total energy of the RPL-DWM is ~14.4X less than SRAM due to small leakage Mat [1] Bank[0]…”

Section: Simulation Setup and Resultsmentioning

confidence: 99%

“…The large cache requires a dense and an energy-efficient memory technology to substitute the current embedded memory solutions like SRAMs and embedded DRAMs (eDRAM) [1]. Emerging high density embedded memories such as Spin-Torque Transfer RAM (STTRAM) [2] are 4-10X denser than the standard SRAM.…”

Section: Introductionmentioning

confidence: 99%

Synergistic circuit and system design for energy-efficient and robust domain wall caches

Motaman

Iyengar

Ghosh

2014

Proceedings of the 2014 International Symposium on Low Power Electronics and Design

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“…There is already a ~2X BW gap between the CPU and external memory today which will worsen if appropriate measures are not taken to fill the BW gap. Emerging high density embedded memories such as embedded DRAM (eDRAM) [1] and Spin Torque Transfer RAM (STTRAM) [2] are 4-10X dense compared to SRAM in order to meet the near term BW requirement. However, future bandwidth intensive applications would need 50-100X denser memories with extremely low standby power.…”

Section: Introductionmentioning

confidence: 99%

Modeling and Analysis of Domain Wall Dynamics for Robust and Low-Power Embedded Memory

Iyengar

Ghosh

2014

Proceedings of the 51st Annual Design Automation Conference

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Non-volatile memories are gaining significant attention for embedded cache application due to low standby power and excellent retention. Domain wall memory (DWM) is one possible candidate due to its ability to store multiple bits/cell in order to break the density barrier. Additionally, it provides low standby power, fast access time, good endurance and good retention. In this paper, we provide a physics-based model of domain wall that comprehends process variations (PV) and Joule heating. The proposed model has been used for circuit simulation. We also propose techniques to mitigate the impact of variability and Joule heating while enabling low-power and high frequency operation.

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Parallel Implementations of Self-Organizing Maps

Hämäläinen¹

2002

Self-Organizing Neural Networks

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Embedded DRAM: more than just a memory

Cited by 12 publications

References 12 publications

Synergistic circuit and system design for energy-efficient and robust domain wall caches

Synergistic circuit and system design for energy-efficient and robust domain wall caches

Modeling and Analysis of Domain Wall Dynamics for Robust and Low-Power Embedded Memory

Parallel Implementations of Self-Organizing Maps

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