The important components of reliability projection are investigated. Acceleration parameters are obtained for a 1.6 nm oxide with a soft breakdown criterion. Based on the physical percolation model, the voltage scaling factor for time to breakdown is found to increase with lower voltage, explaining the experimental observation of 6.7 ± 0.4 dec V −1 for the 1.6 nm oxide. The distribution of breakdown times is shown to be sensitive to thickness variation across the test wafer, and a Weibull slope of 1.38 ± 0.1 was obtained. The temperature dependence of the time to breakdown was found to be non-Arrhenius and to have a slope of 0.02 dec • C −1 . Using these parameters, the 1.6 nm oxide was found to have a 10 year lifetime with a 100 ppm failure rate for 1.3 V operation at 100 • C. Our understanding of soft breakdown is described as well as an investigation of device operation after soft breakdown, which may further improve the reliability projection.

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Absttact ---Multiple tox is thoroughly investigated for nitrogen-implanted gate oxides with the optimization of QBD and a demonstration of 2-GHz counters. Furnace growth at 800°C, 85OoC, and 9OOOC is compared with rapid-thermal-oxidation (RTO) at 105OOC. A wide range of reduced growth rate, 20% to 80%, is achieved that meets the SIA road-map for the next few generations of the CMOS technology. Optimization of charge-to-breakdown (QBD) is achieved through investigation of the nitrogen distribution profile in the oxide that is affected by the growth temperature, nitrogen implant dose, and postoxidation anneals. 101%m2 nitrogen dose results in a higher QB as well as a tighter tail distribution of QBD than 5x10 /cm2 nitrogen dose. The tight distribution of QBD is important for yield improvement. If the oxide is either grown or annealed at 9OO0C, QBD is as good as the QBD of regular oxide without nitrogen. As an example of integration, 0.18-pm CMOS devices with dual gate oxides of 3 nm and 4 nm are fabricated and characterized at 1.5, 1.8, and 2.5 V. Performance of divide-by3 counters is evaluated with the consideration of parasitic RC delays, and the results are superior to the most recently published data. At room temperatures, the maximum toggle frequency (fT) is higher than 2 GHz for both 1.8 and 2.5 V operation, with a power dissipation of 3.4 pW at SOC. To further reduce the power dissipation to 0.08 pW, 1.5-V operation gives 1-GHz fT also at 85OC. A