Engineering ESD Robust LDMOS SCR Devices in FinFET Technology

Lee, Jian–Hsing; Prabhu, Manjunatha; Natarajan, M.

doi:10.1109/led.2018.2838760

Cited by 16 publications

(5 citation statements)

References 11 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…[5] However, a high trigger voltage of common SCR limits its applications in advanced CMOS technology. [6,7] On the other hand, the SCR with a low holding voltage usually faces a latch-up effect. [8,9] Therefore, SCR-based ESD protection devices have been studied over the past few decades.…”

Section: Introductionmentioning

confidence: 99%

Enhancement of holding voltage by a modified low-voltage trigger silicon-controlled rectifier structure for electrostatic discharge protection

Chen¹,

Zhou²,

Jiang³

et al. 2023

Chinese Phys. B

View full text Add to dashboard Cite

Low-voltage trigger silicon-controlled rectifier (LVTSCR) has attracted widespread attention due to its trigger capability at a low voltage range. However, the relatively low holding voltage of traditional LVTSCR potentially increases the risk of latch-up. In this paper, a novel structure of LVTSCR with low trigger voltage and high holding voltage has been proposed for electrostatic discharge (ESD) protection. The proposed ESD protection device possesses an ESD implant and a floating n-well which enhances the current discharge capability of the Gate-grounded NMOS and weakens the current gain of the silicon-controlled rectifier current path. Based on the simulation results, the proposed device retains a low trigger voltage characteristic of LVTSCR and simultaneously increases the holding voltage to 5.53 V, providing an effective way to meet the ESD protection requirement of the 5 V CMOS process.

show abstract

Section: Introductionmentioning

confidence: 99%

Enhancement of holding voltage by a modified low-voltage trigger silicon-controlled rectifier structure for electrostatic discharge protection

Chen¹,

Zhou²,

Jiang³

et al. 2023

Chinese Phys. B

View full text Add to dashboard Cite

show abstract

“…Therefore, an attempt was made to design a protection element that would increase the breakdown voltage and reduce the electric field value. Electrostatic discharge (ESD) [1][2][3][4][5][6][7] can occur because of excessive transient currents, which can be caused by the switching on and off of a power supply, the incomplete grounding of a machine, or human contact with an integrated circuit (IC) through human grounding (i.e., the Human Body Model). Notably, ESD can also irreversibly damage an IC.…”

Section: Introductionmentioning

confidence: 99%

Impacts of Floating Poly on Electrostatic Discharge Protection of Power-Managed High-Voltage Laterally Diffused Metal Oxide Semiconductor Components

Mai

Chen

et al. 2023

Electronics

View full text Add to dashboard Cite

This study used a TSMC 0.18 µm 50 V process to build a high-voltage n-LDMOS structure. In the reference device, the number of floating poly (poly-2) turns was 7, and the width and spacing of each turn was 1 µm. The experiment was realized in three steps, i.e., fixing the number of laps by occupying the width of the structure, adjusting the width of each turn, and adjusting the distance between turns. The first step was fixed to occupy the width of the structure chart to adjust the number of turns. The number of turns increased from 7 to 9 and then decreased to 5 and 3 turns. The reduction in the number of turns resulted in a greater reduction in maximum electric field and an increase in breakdown voltage. A comparison of the 3-turn set with the reference set showed a 42% reduction in maximum electric field, from 4.17 × 103 to 2.46 × 103 (V/cm), and an increase in breakdown voltage (VBK) from 30.2 V to 35.84 V. The second step was to adjust the width of each turn from 1 to 1.4, 1.2, 0.8, and 0.6 µm. This increase in width reduced the maximum electric field, resulting in a greater increase in VBK. When the width was increased to 1.4 µm, the maximum field decreased from 1.95 × 103 V/cm to 1.4 × 103 V/cm and the VBK increased from 30.2 V to 85.6 V, an increase of 183%. The third step was to adjust the per-turn spacing of the reference group from 1 to 1.4, 1.2, 0.8, and 0.6 µm. When the spacing was reduced to 0.6 µm, the maximum electric field decreased by 33% from 1.95 × 103 to 1.32 × 103 V/cm and the VBK increased by 345% from 30.2 to 134.4 V.

show abstract

“…Conventional diode structures and Gate-Grounded NMOS (GGNMOS) structures always require a large silicon area to achieve a good ESD robustness [7][8][9][10]. By contrast, silicon controlled rectifiers (SCRs) have been widely used due to their highest robustness per unit area [11][12][13][14][15][16][17][18][19][20]. However, the unique positive feedback loop of the SCR structure makes it have deep snapback characteristics, which cause a low holding voltage.…”

Section: Introductionmentioning

confidence: 99%

Analysis of current aggregation in gate-control dual direction silicon controlled rectifier

Zhong

Wang

Jin

et al. 2021

IEICE Electron. Express

View full text Add to dashboard Cite

The current aggregation mechanism created by the gate structure is proposed for electrostatic discharging (ESD). Through device simulation, the size-expanded gate structure in gate-control dual-direction silicon controlled rectifier (GC-DDSCR) is found to aggregate the surface parasitic current path and the main SCR current path. The SCR current path is consequently twisted and extended to increase the holding voltage (Vh). Two GC-DDSCRs are fabricated in a 0.5μm CMOS technology and tested by transmission line pulse (TLP). The Vh increases from 13.84V to 16.44V as the gate size expands from 2.5μm to 4.5μm. The mechanism of current aggregation is verified.

show abstract

Engineering ESD Robust LDMOS SCR Devices in FinFET Technology

Cited by 16 publications

References 11 publications

Enhancement of holding voltage by a modified low-voltage trigger silicon-controlled rectifier structure for electrostatic discharge protection

Enhancement of holding voltage by a modified low-voltage trigger silicon-controlled rectifier structure for electrostatic discharge protection

Impacts of Floating Poly on Electrostatic Discharge Protection of Power-Managed High-Voltage Laterally Diffused Metal Oxide Semiconductor Components

Analysis of current aggregation in gate-control dual direction silicon controlled rectifier

Contact Info

Product

Resources

About