Enhanced cluster k-Ary n-cube, a fault-tolerant multiprocessor

Izadi, Baback A.; Özgüner, F.

doi:10.1109/tc.2003.1244942

Cited by 13 publications

(5 citation statements)

References 29 publications

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“…These techniques make the placement stage much easier since we can assume a completely fault-free array, but require a prohibitive amount of redundance if defect rates are too high. It is also interesting to note that techniques for processor arrays such as [Tsuda 2000a;Tsuda and Shimizu 2000;Tsuda 2000b;Izadi and Ozguner 2003] share a common theme with device-level schemes in FPGAs.…”

Section: Related Workmentioning

confidence: 99%

The survivability of design-specific spare placement in FPGA architectures with high defect rates

Agarwal

Cong

Tagiku

2013

ACM Trans. Des. Autom. Electron. Syst.

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We address the problem of optimizing fault tolerance in FPGA architectures with high defect rates (such as nano-FPGAs) without significantly degrading performance. Our methods address fault tolerance during the placement and reconfiguration stages of FPGA programming. First, we provide several complexity results for both the fault reconfiguration and fault-tolerance placement problems. Then, we propose a placement algorithm which, in the presence of randomly generated faults, optimizes spare placement to maximize the probability that the FPGA can be reconfigured to meet a specified timing constraint. We also give heuristics for reconfiguration after faults have been detected. Despite the hardness results for both the placement and reconfiguration problems, we show our heuristics perform well in simulation (in one scenario, increasing the probability of successful reconfiguration by as much as 55% compared to a uniform spare placement). ACM Reference Format:Agarwal, A., Cong, J., and Tagiku, B. 2013. The survivability of design-specific spare placement in FPGA architectures with high defect rates.

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Section: Related Workmentioning

confidence: 99%

The survivability of design-specific spare placement in FPGA architectures with high defect rates

Agarwal

Cong

Tagiku

2013

ACM Trans. Des. Autom. Electron. Syst.

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“…In this case, the only solution is that the rightmost three faulty columns must be replaced by the three redundant columns and the rest of the faulty cells must be replaced by the two SRs. This concept can also be used in the fault-tolerant design of k-ary n-cube multiprocessors (Izadi and Ozguner 2003) and the mass storage system (Choi, Park, Piceri, and Lombardi 2005).…”

Section: Introductionmentioning

confidence: 99%

Optimal cutting design and analysis for fault-tolerant scheme of redundant memories

Huang

Chang

Fang

2010

International Journal of Systems Science

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Fault-tolerant design for memory production is beginning to play an important role in increasing the yield rate of manufacturing. To improve the reliability of memory manufacturing, there are many methods that have been proposed. One of the most used technologies is replacing the faulty cells with spare memory interleaved in the memory. Nowadays, laser-cutting technology improves the yield of memories because of the enhancement of the use of spare lines. However, the issue of choosing a cutting location significantly affects the utilisation of spare lines. A bad cutting location can even render it useless. To use spare lines more efficiently, this article proposes two algorithms. The first one is designed to seek out a good cutting location. It corrects some defects of previous algorithms and provides a better approach to finding cutting candidates. In addition, because most heuristic solution-finding algorithms do not work properly under the condition of cutting memory, the second algorithm, called modification of most-repair is proposed to help make the decision as to whether or not a solution exists for the faulty pattern. We can find an optimal solution by combing these two algorithms. The experimental results show that our proposed algorithms increase the reparable percentage of a 1024-by-1024 memory from 55 to 100% and also improve both the reliability of memory manufacturing and the flexibility of spare lines.

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“…Related research in architectural-level fault tolerance schemes for processors based on CMOS technology include [7,8,9,10]. However, these schemes deal with a low and relatively fixed fault rate and are not applicable to the nanoelectronic environment.…”

Section: Introductionmentioning

confidence: 99%

Fault tolerant nanoelectronic processor architectures

Rao¹,

Orailoğlu²,

Karri³

2005

Proceedings of the 2005 Conference on Asia South Pacific Design Automation - ASP-DAC '05

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In this paper we propose a fault-tolerant processor architecture and an associated fault-tolerant computation model capable of fault tolerance in the nanoelectronic environment that is characterized by high and time varying fault rates. The proposed fault tolerant processor architecture not only guarantees the correctness of computation but also is flexible in that it dynamically trades-off computation resources and performance. The core of the architecture is a decentralized instruction control unit called the voter that achieves both fault tolerance and the maximum parallel execution of instructions by exploiting the abundant computational resources provided by nanotechnologies. Although the result of each instruction needs to be confirmed by executing it on multiple computation units, multiple unconfirmed instructions can proceed as speculative branches. The voter implements a hardware-frugal computation unit allocation algorithm to organize the redundant computations and to dynamically control the growth of speculative branches.

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Enhanced cluster k-Ary n-cube, a fault-tolerant multiprocessor

Cited by 13 publications

References 29 publications

The survivability of design-specific spare placement in FPGA architectures with high defect rates

The survivability of design-specific spare placement in FPGA architectures with high defect rates

Optimal cutting design and analysis for fault-tolerant scheme of redundant memories

Fault tolerant nanoelectronic processor architectures

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