Epitaxial Ge-on-Nothing and Epitaxial Ge on Si-on-Nothing as Virtual Substrates for 3D Device Stacking Technologies

Loo, Roger; Porret, Clément; Han, Hyo Jin; Srinivasan, Ashwyn; Vecchio, E.; Depauw, Valérie

doi:10.1149/2162-8777/ac1a0b

Cited by 4 publications

(2 citation statements)

References 25 publications

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“…An in-house fabricated epitaxially grown Ge virtual substrate (VS) [11] was used to optimize the ECCI measurement routine. The thickness of the Ge VS layer is ~1 μm and the expected TDD is ~2-5e7 cm -2 [11][12]. This TDD is significantly higher compared to the TDD of the Si1-xGex SRBs.…”

Section: Methodsmentioning

confidence: 99%

Application and Optimization of Automated ECCI Mapping to the Analysis of Lowly Defective Epitaxial Films on Blanket or Patterned Wafers

Han

Hantschel

Lagrain

et al. 2021

International Symposium for Testing and Failure Analysis

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The physical limits of CMOS scaling, as predicted by Moore's Law, should have already been reached several years ago. However, the scaling of transistors is still ongoing due to continuous improvements in material quality enabling the fabrication of complex device structures with nm-size dimensions. More than ever, the structural properties and the eventual presence of crystalline defects in the various semiconductor materials (SiGe, III/V) play a critical role. Electron channeling contrast imaging (ECCI) is a powerful defect analysis technique developed in recent years. The technique allows for fast and non-destructive characterizations with the potential for extremely low detection limits. The analysis of lowly defective materials requires measurements over large areas to obtain statistically relevant data. Automated ECCI mapping routines enable the quantification of crystalline defect densities as low as ~1e5 cm-2, e.g., Si0.75Ge0.25 strain relaxed buffers (SRB) epitaxially grown on a Si substrate. Methods to reduce the total measurement time without compromising its sensitivity will be discussed. The measurement routine has also been optimized to detect extended crystalline defects in III/V layers, selectively grown on shallow trench isolation patterned Si wafers. Throughout these examples, this study demonstrates the great potential of ECCI as a versatile and industry-relevant technique for defect analysis.

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Section: Methodsmentioning

confidence: 99%

Application and Optimization of Automated ECCI Mapping to the Analysis of Lowly Defective Epitaxial Films on Blanket or Patterned Wafers

Han

Hantschel

Lagrain

et al. 2021

International Symposium for Testing and Failure Analysis

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“…Recently, two labs have reported the successful fabrication of a Ge-on-Nothing (GeON) structure based on the reorganization of macro-porous Ge at high temperatures. 39,40) This method is based on the Si-on-Nothing fabrication suggested by Mizushima et al 41) The GeON fundamental fabrication procedure is shown in Fig. 1.…”

Section: Introductionmentioning

confidence: 99%

Ge-on-insulator fabrication based on Ge-on-nothing technology

Yamamoto,

Wang,

Loo

et al. 2024

Jpn. J. Appl. Phys.

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Ge-on-Insulator (GOI) is considered a necessary structure for novel Ge-based devices. This paper proposes an alternative approach for fabricating GOI based on the Ge-on-Nothing (GeON) template. In this approach a regular macropore array is formed by lithography and dry etching. These pores close and merge upon annealing, forming a suspended monocrystalline Ge membrane on one buried void. GOI is fabricated by direct bonding of GeON on Si carrier substrates, using an oxide bonding interface, and subsequent detachment. The fabricated GOI shows uniform physical properties as demonstrated using micro-photoluminescence measurements. Its electrical characteristics and cross-sectional structure are superior to those of Smart-CutTM GOI. To demonstrate its application potential, back-gate GOI capacitor and MOSFETs are fabricated. Their characteristics nicely agree with the theoretically calculated one and show typical MOSFET operations, respectively, which indicates promising Ge crystallinity. This method, therefore, shows the potential to provide high-quality GOI for advanced Ge application devices.

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Heterogeneous 3-D Sequential CFETs With Ge (110) Nanosheet p-FETs on Si (100) Bulk n-FETs

Kim,

Lim,

Jeong

et al. 2024

IEEE Trans. Electron Devices

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Epitaxial Ge-on-Nothing and Epitaxial Ge on Si-on-Nothing as Virtual Substrates for 3D Device Stacking Technologies

Cited by 4 publications

References 25 publications

Application and Optimization of Automated ECCI Mapping to the Analysis of Lowly Defective Epitaxial Films on Blanket or Patterned Wafers

Application and Optimization of Automated ECCI Mapping to the Analysis of Lowly Defective Epitaxial Films on Blanket or Patterned Wafers

Ge-on-insulator fabrication based on Ge-on-nothing technology

Heterogeneous 3-D Sequential CFETs With Ge (110) Nanosheet p-FETs on Si (100) Bulk n-FETs

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