Experiences with parametric BIST for production testing PLLs with picosecond precision

Kinger, Rakesh; Narasimhawsamy, Swetha; Sunter, Stephen

doi:10.1109/test.2010.5699243

Cited by 13 publications

(4 citation statements)

References 8 publications

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“…The accuracy of test results and the test cost are dependent on the selection of validated functional specifications. However, the tight feedback characteristic of PLL makes this solution less attractive because it is difficult to relate the specifications from the PLL level to the block level, which requires high‐performance instruments with even unacceptable test cost. On‐chip jitter measurement [11–14]. …”

Section: Previous Workmentioning

confidence: 99%

All‐digital built‐in self‐test scheme for charge‐pump phase‐locked loops

Xia

Tang

2020

IET Circuits, Devices & Syst

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Charge‐pump phase‐locked loop (CP‐PLL) is widely used to generate timing signals in systems on chips (SoCs). However, the number of cores embedded in SoCs, the limited I/O port resources and the cost of external test equipment lead to the increase of test complexity and cost. An all‐digital built‐in self‐test structure of CP‐PLL especially suitable for low‐cost production tests when I/O port resources are limited is proposed. The structure is simple and easily implemented with just a few DFFs, MUXs and some existing circuits in CP‐PLL under test. It reduces the requirement of additional external test clocks and high‐performance test equipment, which decreases the test cost of the whole integrated circuits. Combined with the proposed calibration technique, it eliminates the effect of uncertain initial value of voltage controlled oscillator input voltage on the fault coverage. Thus, the reliability of test results is also increased. Experiment results demonstrate the effectiveness of the proposed scheme with high fault coverage of 99.16%. In addition, the physical chip design is presented to show low area overhead of 1.37%.

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Section: Previous Workmentioning

confidence: 99%

All‐digital built‐in self‐test scheme for charge‐pump phase‐locked loops

Xia

Tang

2020

IET Circuits, Devices & Syst

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“…Apart from the commonly used FLT, the literature [2] allows the estimation of forward path gain and measures the effects of leakage and mismatch. The paper [3] describes a PLL BIST scheme that is capable of testing all timing parameters of PLLs in production ICs such as jitter, duty cycle, phase delay, frequency ratio, and locking time. However, the PLL circuit is hard to describe, and it is difficult to evaluate the performance of the parameters extracted from the signals directly.…”

Section: Previous Workmentioning

confidence: 99%

A Hybrid Low-Cost PLL Test Scheme based on BIST Methodology

Cai¹,

Que²,

Liu³

et al. 2015

Advances in Intelligent Systems Research

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In this paper, a hybrid built-in self-test (BIST) scheme is firstly proposed for phase-locked loop (PLL) production test and performance characterization. The scheme combines the structure test and function test in production test operation. The former is to detect hard faults and the latter is used to improve the soft fault coverage. Jitter measurement is selected as a typical parameter test in performance characterization mode, which includes vernier delay line (VDL) to measure timing jitter and undersampling technology to measure cycle-cycle jitter. The goal of the scheme is to enable complete production quality test and exact performance characterization.

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“…PLL (Phase-Locked Loop) is one of the important modules in high speed communication system [1]. However the traditional testing methods have been unable to meet the test requirements, BIJM (Built-in jitter measurement) is becoming more and more important in the PLL testing [2,3]. BIJM technology includes capacitor charging measurement circuit [4], vernier delay line (VDL) measurement circuit [5], time amplification measurement circuit [6], undersampling measurement circuit [7], and so on.…”

Section: Introductionmentioning

confidence: 99%

An improved BIJM circuit based on undersampling technique

Cai

Xiao

et al. 2018

IEICE Electron. Express

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An improved BIJM (Built-in jitter measurement) circuit is presented in this paper, which is consisted of three improvement points. Firstly, multi-phase sampling technology improves the sampling efficiency based on the specially designed multi-phase clock generation circuit. Secondly, the median-edge alignment is used as the new jitter extraction method, which is taking the place of the mean-edge alignment. This method can filter lowfrequency noise component to extract the cycle-to-cycle jitter. Thirdly, single-edge accumulation data processing method accumulates one edge in each cycle, blocking the correlation of adjacent sampling location, which can improve measurement accuracy and save the area overhead. The proposed jitter measurement circuit is designed at SMIC 40 nm CMOS process, and the circuit occupies a total silicon area of 9108 um 2 . Post-layout simulation results show the measurement error is only 0.94%.

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Experiences with parametric BIST for production testing PLLs with picosecond precision

Cited by 13 publications

References 8 publications

All‐digital built‐in self‐test scheme for charge‐pump phase‐locked loops

All‐digital built‐in self‐test scheme for charge‐pump phase‐locked loops

A Hybrid Low-Cost PLL Test Scheme based on BIST Methodology

An improved BIJM circuit based on undersampling technique

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