Experimental and simulation results on Si integrated inductor efficiency for smart RF-ICs

Royet, A.S.; Barbé, J. C.; Valorge, Olivier; Constant, I.

doi:10.1109/icecs.2014.7049998

Cited by 8 publications

(5 citation statements)

References 6 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…High resistivity substrates (e.g. glass) can effectively suppress parasitic capacitance between devices placed on the chip and silicon substrate [51], [56].…”

Section: Silicon On Insulator (Soi)mentioning

confidence: 99%

“…Parasitic parallel capacitance between the integrated inductor and substrate 𝐶 Ind | |Sub should be suppressed by any means since it represents causes of power losses in the circuit. Efficient methods to counter the capacitive losses include: using very high-resistivity substrate, very low-resistivity substrate [52], Patterned Ground Shields [50][51][52] or locating the inductor as far away from the substrate as possible. Parasitic parallel capacitance between the integrated capacitor and substrate 𝐶 Cap| |Sub could also be the reason of further power dissipation in the circuit, especially, when the capacitor is implemented in the circuit as flying device not connected to the substrate potential.…”

Section: Comparison To Mls Structures With Inductor and Capacitormentioning

confidence: 99%

See 1 more Smart Citation

An Overview of Fully On-Chip Inductors

Ondica¹,

Kovac²,

Hudec³

et al. 2023

RADIOENGINEERING

View full text Add to dashboard Cite

This paper focuses on full integration of passive devices, especially inductors with emphasis on multi-layer stacked (MLS) structures of fully integrated inductors using patterned ground shield (PGS) and fully integrated capacitor. Comparison of different structures is focused on the main electrical parameters of integrated inductors (e.g. inductance 𝐿, inductance density 𝐿 𝐴 , quality factor 𝑄, frequency of maximum quality factor 𝐹 𝑄max , self-resonant frequency FSR, and series resistance 𝑅 DC ) and other non-electrical parameters (e.g. required area, manufacturing process, purpose, etc.) that are equally important during comparison of the structures. Categorization of inductor structures with most significant results that was reported in the last years is proposed according to manufacturing process. Final geometrical and electrical properties of the structure in great manner accounts to the fabrication process of integrated passive device. This work offers an overview and state-of-the-art of the integrated inductors as well as manufacturing processes used for their fabrication. Second purpose of this paper is insertion of the proposed structure from our previous work among the other results reported in the last 7 years. With the proposed solution, one can obtain the highest inductance density 𝐿 𝐴 = 23.59 nH/mm 2 and second highest quality factor 𝑄 = 10.09 amongst similar solutions reported in standard technologies that is also suitable competition for integrated inductors manufactured in advanced technology nodes.

show abstract

“…High resistivity substrates (e.g. glass) can effectively suppress parasitic capacitance between devices placed on the chip and silicon substrate [51], [56].…”

Section: Silicon On Insulator (Soi)mentioning

confidence: 99%

Section: Comparison To Mls Structures With Inductor and Capacitormentioning

confidence: 99%

An Overview of Fully On-Chip Inductors

Ondica¹,

Kovac²,

Hudec³

et al. 2023

RADIOENGINEERING

View full text Add to dashboard Cite

show abstract

“…With utilizing special layout techniques (e.g. Horizontal Parallelization [38], Slicing [39], Tapering [40], Equal Path Lengths (EPL) [41], Patterned Ground Shield (PGS) [42], [43] and others), the inductor properties can be optimized to comply with requirements in these technologies as well [8], [20], [22]- [24]. These techniques can effectively suppress undesirable parasitic effects present in on-chip inductors caused mostly by high frequency signal (e.g.…”

Section: A Standard General Purpose Technologiesmentioning

confidence: 99%

“…Higher resistivity decreases energy losses in substrate caused by parasitic capacitance between devices and silicon substrate [45]. This process can significantly reduce substrate losses and improve the performance of integrated devices [43], [46].…”

Section: Silicon On Insulatormentioning

confidence: 99%

Fully Integrated On-Chip Inductors: An Overview

Robert

Kovac

Richard

et al. 2022

2022 20th International Conference on Emerging eLearning Technologies and Applications (ICETA)

View full text Add to dashboard Cite

This paper presents an overview and State-of-the-Art of fully integrated inductors with common fabrication processes used for implementation of these structures into a chip. The first step is an overview of fabrication technologies that starts with standard CMOS general purpose processes expanded by Far-BEOL and substrate alteration process (SOI, Silicon Embedded, TSV, TGV, PTH, Core Insertion); and continues to advanced process nodes like SMMT and Bond Wire utilization. Then, an overview of fully integrated inductor structures consists of selected topologies with notable parameters achieved in last few years. Critical parameters of integrated inductors include: inductance L DC , inductance density L A , quality factor Q, selfresonant frequency FSR and series resistance R DC . These parameters are as important as the purpose and fabrication process.

show abstract

“…Particularly, the effect of the substrate characteristics on the PGS efficiency has been investigated 8,9,10 . Specifically, in 10 it is claimed that the shield is able to improve the Q peak if the substrate resistivity, ρ Si , lays between 1 Ω ⋅ cm and 100 Ω ⋅ cm. For above reasons, nanometer CMOS design kits always include the PGS in all the available libraries of both inductors and transformers.…”

Section: Introductionmentioning

confidence: 99%

The effect of a metal PGS on the Q ‐factor of spiral inductors for RF and mm‐wave applications in a 28‐nm CMOS technology

Spataro

Papotto

Ragonese

2020

Int J RF Microw Comput Aided Eng

View full text Add to dashboard Cite

In this paper, the effect of a metal patterned ground shield (PGS) on the performance of monolithic inductors is investigated. To this aim, three spiral inductors integrated in a 28‐nm fully depleted (FD) silicon‐on‐insulator (SOI) CMOS technology are analyzed by means of a 3‐D FEM‐based commercial software. The inductors have been designed at different operating frequencies in the RF and mm‐wave ranges to better explore the effect of the PGS. Extensive analysis revealed that the shield is able to improve the quality factor (Q‐factor) only of the inductor operated at the lowest frequency (ie, K‐band). On the contrary, it has a detrimental effect on the Q‐factor of the inductors working at higher frequencies. This is mainly due to induced losses in the PGS itself, which are so high to frustrate the substrate loss reduction. This result gives a different perspective to the adoption of the PGS for CMOS integrated inductors, which is largely recommended to improve inductor performance in the current state of the art.

show abstract

Experimental and simulation results on Si integrated inductor efficiency for smart RF-ICs

Cited by 8 publications

References 6 publications

An Overview of Fully On-Chip Inductors

An Overview of Fully On-Chip Inductors

Fully Integrated On-Chip Inductors: An Overview

The effect of a metal PGS on the Q ‐factor of spiral inductors for RF and mm‐wave applications in a 28‐nm CMOS technology

Contact Info

Product

Resources

About