Fault models for embedded-DRAM macros

Chao, Mango C.-T.; Yang, Haoyu; Huang, Rei-Fu; Lin, Shih-Chin; Chin, Ching-Yu

doi:10.1145/1629911.1630097

Cited by 11 publications

(12 citation statements)

References 10 publications

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“…Whereas A modules did not favor one direction over the other, B and C modules heavily favored '1' '0' errors. Averaged on a module-by-module basis, the relative fraction of '1' '0' errors is 49.9%, 92.8%, and 97.1% for A, B, and C. 15 The seemingly asymmetric nature of disturbance errors is related to an intrinsic property of DRAM cells called orientation. Depending on the implementation, some cells represent a logical value of '1' using the charged state, while other cells do so using the discharged state -these cells are referred to as true-cells and anti-cells, respectively [44].…”

Section: Data Pattern Dependencementioning

confidence: 99%

“…We hypothesize, based on past studies and findings, that there may be three ways of interaction.2 First, changing the voltage of a wordline could inject noise into an adjacent wordline through 2At least one major DRAM manufacturer has confirmed these hypotheses as potential causes of disturbance errors. electromagnetic coupling [15,49,55]. This partially enables the adjacent row of access-transistors for a short amount of time and facilitates the leakage of charge.…”

Section: Mechanics Of Disturbance Errorsmentioning

confidence: 99%

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Flipping bits in memory without accessing them: An experimental study of DRAM disturbance errors

Kim¹,

Daly²,

Kim³

et al. 2014

2014 ACM/IEEE 41st International Symposium on Computer Architecture (ISCA)

449

1,019

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Abstract. Memory isolation is a key property of a reliable and secure computing system -an access to one memory address should not have unintended side effects on data stored in other addresses. However, as DRAM process technology scales down to smaller dimensions, it becomes more difficult to prevent DRAM cells from electrically interacting with each other. In this paper, we expose the vulnerability of commodity DRAM chips to disturbance errors. By reading from the same address in DRAM, we show that it is possible to corrupt data in nearby addresses. More specifically, activating the same row in DRAM corrupts data in nearby rows. We demonstrate this phenomenon on Intel and AMD systems using a malicious program that generates many DRAM accesses. We induce errors in most DRAM modules (110 out of 129) from three major DRAM manufacturers. From this we conclude that many deployed systems are likely to be at risk. We identify the root cause of disturbance errors as the repeated toggling of a DRAM row's wordline, which stresses inter-cell coupling effects that accelerate charge leakage from nearby rows. We provide an extensive characterization study of disturbance errors and their behavior using an FPGA-based testing platform. Among our key findings, we show that (i) it takes as few as 139K accesses to induce an error and (ii) up to one in every 1.7K cells is susceptible to errors. After examining various potential ways of addressing the problem, we propose a low-overhead solution to prevent the errors.

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Section: Data Pattern Dependencementioning

confidence: 99%

Section: Mechanics Of Disturbance Errorsmentioning

confidence: 99%

Flipping bits in memory without accessing them: An experimental study of DRAM disturbance errors

Kim¹,

Daly²,

Kim³

et al. 2014

2014 ACM/IEEE 41st International Symposium on Computer Architecture (ISCA)

449

1,019

View full text Add to dashboard Cite

show abstract

“…Also, March H2C did not mention how many hammering times are sufficient to detect the targeted partial faults, which makes the effectiveness and the occasion to apply March H2C unclear. [14] reported another fault requiring a hammering test to detect, i.e., the word-line coupling fault. When a word-line coupling fault occurs, turning on one word-line may slightly turn on its adjacent word-line due to an unexpected large coupling capacitance in between and hence may leak the stored value on the adjacent word-line.…”

Section: Overview Of the Edram Macro In Usementioning

confidence: 99%

“…[13] listed the potential functional fault models of DRAMs and proposed their corresponding tests. [14] discussed the targeted fault models for eDRAMs. None of the previous works reported the physical defects that results in the targeted faults in practice except [15], which discussed the physical defect, simulation model, and test reduction for the strap problem in DRAMs.…”

Section: Introductionmentioning

confidence: 99%

“…Several hammering test algorithms were presented by [12] [13] [14] and can be used to detect a weak data retention fault linked with a coupling fault, partial faults, or wordline coupling fault in DRAMs or eDRAMs. After repeatedly reading/writing (hammering) an adjacent aggressor row or column which couples the victim cell, the value stored in the victim cell may be leaked out before the next refresh.…”

Section: Introductionmentioning

confidence: 99%

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Alternate hammering test for application-specific DRAMs and an industrial case study

Huang

Yang

Chao

et al. 2012

Proceedings of the 49th Annual Design Automation Conference

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This paper presents a novel memory test algorithm, named alternate hammering test, to detect the pairwise word-line hammering faults for application-specific DRAMs. Unlike previous hammering tests, which require excessively long test time, the alternate hammering test is designed scalable to industrial DRAM arrays by considering the array layout for potential fault sites and the highest DRAM-access frequency in real system applications. The effectiveness and efficiency of the proposed alternate hammering test are validated through the test application to an eDRAM macro embedded in a storage-application SoC.

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Accumulator-based self-adjusting output data compression for embedded word-organized DRAMs

Voyiatzis¹,

Efstathiou²,

Sgouropoulou³

2014

2014 9th IEEE International Conference on Design &Amp; Technology of Integrated Systems in Nanoscale Era (DTIS)

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An approach for periodic online testing of embedded DRAMs is presented. The fault-free memory contents are compressed, using accumulator-based response compaction, and periodically compared to subsequently compressed test data. The compressed signature is updated concurrently with write operations, without need for recomputing. Comparisons with previously proposed schemes indicate that the proposed scheme results in considerable savings in hardware overhead.

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Fault models for embedded-DRAM macros

Cited by 11 publications

References 10 publications

Flipping bits in memory without accessing them: An experimental study of DRAM disturbance errors

Flipping bits in memory without accessing them: An experimental study of DRAM disturbance errors

Alternate hammering test for application-specific DRAMs and an industrial case study

Accumulator-based self-adjusting output data compression for embedded word-organized DRAMs

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