FDSOI CMOS devices featuring dual strained channel and thin BOX extendable to the 10nm node

Simulation Study of the Impact of Quantum Confinement on the Electrostatically Driven Performance of n-type Nanowire Transistors

“…This research and corresponding technology development has culminated in the introduction of 28-nm fully depleted silicon-on-insulator (FDSOI) CMOS by STMicroelectronics [17] and 22-and 14-nm FinFET CMOS by Intel [18] and Samsung [19]. It has been speculated that the scalability of FDSOI can extend planar CMOS technology down to 10 nm [20], and FinFETs can extend CMOS technology down to 7 nm [21]. Even better electrostatic integrity, offered by gate-all-around nanowire transistor (NWT) architectures [8]- [10] may be needed to extend CMOS scaling beyond the 7-nm mark [22].…”

Fully depleted SOI (FDSOI) technology

“…The degradation of the intrinsic FinFET transistor performance should not be surprising due to diminishing effectiveness of strain and increase of parasitic resistance in highly scaled FinFET. Contrary to the common misconception, high performance FDSOI devices have been demonstrated by using intrinsically strained channels, i.e., tensily strained silicon for NFET and compressively strained SiGe for PFET [30,32,59]. As shown in Figures 10 and 11, at V DD = 0.9 V and I OFF = 100 nA/µm, I EFF is 820 µA/µm and 615 µA/µm for NFET and PFET, respectively.…”

Mobility of Circular and Elliptical Si Nanowire Transistors Using a Multi-Subband 1D Formalism

“…In recent years, there has been a huge interest in the study and the modelling of the impact of material and geometrical features of Gate-all-around (GAA) nanowire transistors (NWTs) [1]- [5]. They are being considered as potential candidates to extend the CMOS technology beyond the 7 nm node [6] due to the better electrostatic integrity compared to Fully-Depleted Silicon-On-Insulator (FDSOI) [7] transistors and FinFETs [8]. To underpin these technology projections, it is important to study the impact of the NWT cross-sectional shape at the scaling limit on the transistor performance.…”