Feasibility Study of Composite Dielectric Tunnel Barriers for Flash Memory

Verma, S.; Pop, Eric; Kapur, Pawan; Majhi, P.; Parat, Krishna; Saraswat, Krishna C.

doi:10.1109/drc.2007.4373662

Cited by 4 publications

(9 citation statements)

References 3 publications

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“…Reduction of the thickness of the tunnel oxide may solve this challenge, but it also presents a severe bottleneck due to stress-induced leakage current (SILC). Many reports document the tunnel oxide should not reduce beyond 7-8nm because of the tradeoff between P/E process and retention reliability [3][4]. This condition will restrict the betterment of the device performance in terms P/E voltage and time.…”

Section: Introductionmentioning

confidence: 99%

“…As one of the effective solutions, the inception of the different dielectric with high dielectric constant (high-k) materials stacks to engineer the tunnel oxide is proposed. Many researches have been reported about the tunnel barrier engineering (TBE) approach to analyze the performance before and after the inception of high-k dielectric materials [1][2][3][4]. TBE technology is an approach to modify the tunnel barrier by incorporating the high-k dielectric materials in which the high-k dielectric will extend scalability of the same equivalent oxide thickness (EOT) by applying a thicker physical tunnel stack.…”

Section: Introductionmentioning

confidence: 99%

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Optimization of high-k composite dielectric materials of variable oxide thickness tunnel barrier for nonvolatile memory

A.Hamid

Hamzah

Alias

et al. 2019

IJEECS

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Downscaling the tunnel oxide thickness has become one of the innovative solutions to minimize the operational voltage with better the programming/erasing (P/E) operation time. However, the downscaling technique faces several challenges where the conventional SiO2 tunnel layer has reached its limit. But a practical alternative has been introduced; Variable Oxide Thickness (VARIOT) technology in flash memory has been promising. VARIOT is one of tunnel barrier engineering technology for incorporating the high-k dielectric materials as a composite tunnel barrier. This paper presents the VARIOT concept to determine the optimum set of combination, the equivalent oxide thickness (EOT) and the low-k oxide thickness (Tox) for alternate high-k materials. Fowler-Nordheim (F-N) tunneling coefficients are also extracted for various combinations of VARIOT, where in this work ZrO2, HfO2, Al2O3, La2O3, and Y2O3 are used. The VARIOT optimization is conducted using 3-Dimensional (3D) Silicon Nanowire Field-Effect-Transistor (SiNWFET) device structure and simulated in TCAD Simulation tools. From the simulation results, it has found out that the high-k materials of La2O3 asymmetric stack is the excellent dielectric material among four (4) other dielectric materials; ZrO2, HfO2, Al2O3 and Y2O3 for EOT=4nm and Tox=1nm.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Optimization of high-k composite dielectric materials of variable oxide thickness tunnel barrier for nonvolatile memory

A.Hamid

Hamzah

Alias

et al. 2019

IJEECS

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“…Following Verma et al, the flash memory constraints are given as in Table I. 14) These constraints responsible in limiting the allowed T ox range for each EOT, resulting in a domain down-selection.…”

Section: Simulation Proceduresmentioning

confidence: 99%

“…For simplicity, another feature that can be used to assess the performance of VARIOT is the slope of the J-V curve. Because the nonlinear behavior of VARIOT can be defined by the slope of the J-V curve, 14) by using exponential fitting of J g = A · exp(BV fg ), the slope between zero bias to program constraint of the J-V curve were extracted as shown in the inset. Parameter A is the intercept at y-axis and B is the slope of the semilog plot.…”

Section: Device Characterization Of Gaa-fg With Variot Tunnel Layermentioning

confidence: 99%

“…In this work, four different high-k materials (i.e., Si 3 N 4 , Al 2 O 3 , HfO 2 , and ZrO 2 ) were explored using the DQT model as these materials can be deposited on SiO 2 layer. [22][23][24] After these matters were clarified, the optimization was performed based on proposed method by Verma et al 14) For simplicity, the optimization was conducted using MOS capacitor (MOSCap) structure, in which to fairly assess the electrical behavior of the VARIOT combinations. The equivalent oxide thickness (EOT) of asymmetric VARIOT is fixed for 4 : 1 : 8 nm while varying its low-k thickness, Tox from 1 nm to the corresponding EOT.…”

Section: Simulation Proceduresmentioning

confidence: 99%

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Low-voltage high-speed programming gate-all-around floating gate memory cell with tunnel barrier engineering

Hamzah

Alias

Ismail

2018

Jpn. J. Appl. Phys.

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The aim of this study is to investigate the memory performances of gate-all-around floating gate (GAA-FG) memory cell implementing engineered tunnel barrier concept of variable oxide thickness (VARIOT) of low-k/high-k for several high-k (i.e., Si 3 N 4 , Al 2 O 3 , HfO 2 , and ZrO 2 ) with low-k SiO 2 using three-dimensional (3D) simulator Silvaco ATLAS. The simulation work is conducted by initially determining the optimized thickness of low-k/ high-k barrier-stacked and extracting their Fowler-Nordheim (FN) coefficients. Based on the optimized parameters the device performances of GAA-FG for fast program operation and data retention are assessed using benchmark set by 6 and 8 nm SiO 2 tunnel layer respectively. The programming speed has been improved and wide memory window with 30% increment from conventional SiO 2 has been obtained using SiO 2 / Al 2 O 3 tunnel layer due to its thin low-k dielectric thickness. Furthermore, given its high band edges only 1% of charge-loss is expected after 10 years of %3.6/3.6 V gate stress.

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Floating gate potential of gate-all-around floating gate memory cell: parameter extraction and compact model

Hamzah,

Alias,

Johari

et al. 2024

Phys. Scr.

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The compact modeling of NAND flash memories is crucial for integrated circuit designers to carry out efficient and precise circuit-level evaluations, particularly in the case of 3D NAND flash where the 3D geometry leads to significant parasitic coupling impacts on performance. In this work, we proposed a charge-based modeling approach for gate-all-around floating gate memory cells. The compact model is based on the derived unified charge control model where the mobile charge is explicitly solved. By solving the charge balance model and taking into account voltage-dependent parasitic capacitances for accurate coupling effects, the floating gate potential is accurately computed. The simulation results are validated with numerical TCAD simulation and showed good agreement with TCAD simulation. By solving the charge balance model and considering voltage-dependent parasitic capacitances for more accurate coupling effects, the floating gate potential is accurately calculated. The simulation results were validated using numerical TCAD simulation and showed good agreement, demonstrating that the floating gate potential is accurately estimated through the inclusion of voltage-dependent parasitic capacitances. Additionally, the results indicate that subthreshold degradation is caused by interface trap charge in the experimental device, and the proposed model successfully replicates experimental data.

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Feasibility Study of Composite Dielectric Tunnel Barriers for Flash Memory

Cited by 4 publications

References 3 publications

Optimization of high-k composite dielectric materials of variable oxide thickness tunnel barrier for nonvolatile memory

Optimization of high-k composite dielectric materials of variable oxide thickness tunnel barrier for nonvolatile memory

Low-voltage high-speed programming gate-all-around floating gate memory cell with tunnel barrier engineering

Floating gate potential of gate-all-around floating gate memory cell: parameter extraction and compact model

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