Finfet with isolated n+ and p+ gate regions strapped with metal and polysilicon

Mathew,; Sadd,; White,; Vandooren,; Dakshina-Murthy,; Cobb,; Stephens,; Mora, J.; Pham,; Conner,; Shi, Jianrong; Thean,; Barr,; Zavala,; Schaeffer,; Rendon,; Sing,; Orlowski,; Nguyen, Nguyen; Mogab,

doi:10.1109/soi.2003.1242918

Cited by 6 publications

(3 citation statements)

References 2 publications

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“…However, the workfunctions can also be made different. This leads to an asymmetric gate-workfunction SG FinFET or ASG FinFET ( Figure 6) [86,87]. ASG FinFETs can be fabricated with selective doping of the two gate-stacks.…”

Section: Finfet Classificationmentioning

confidence: 99%

FinFETs: From Devices to Architectures

Bhattacharya

Jha

2014

Advances in Electronics

164

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Since Moore’s law driven scaling of planar MOSFETs faces formidable challenges in the nanometer regime, FinFETs and Trigate FETs have emerged as their successors. Owing to the presence of multiple (two/three) gates, FinFETs/Trigate FETs are able to tackle short-channel effects (SCEs) better than conventional planar MOSFETs at deeply scaled technology nodes and thus enable continued transistor scaling. In this paper, we review research on FinFETs from the bottommost device level to the topmost architecture level. We survey different types of FinFETs, various possible FinFET asymmetries and their impact, and novel logic-level and architecture-level tradeoffs offered by FinFETs. We also review analysis and optimization tools that are available for characterizing FinFET devices, circuits, and architectures.

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Section: Finfet Classificationmentioning

confidence: 99%

FinFETs: From Devices to Architectures

Bhattacharya

Jha

2014

Advances in Electronics

164

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“…AWSG FinFETs can be fabricated using differently doped gate stacks without the need for additional masking steps [Kedzierski et al 2001;Mathew et al 2003]. ADSG FinFETs require an extra mask to dope the source and drain unequally [Moradi et al 2011].…”

Section: Discussionmentioning

confidence: 99%

Ultra-low-leakage, Robust FinFET SRAM Design Using Multiparameter Asymmetric FinFETs

Guler

Jha

2016

J. Emerg. Technol. Comput. Syst.

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Memory arrays consisting of Static Random Access Memory (SRAM) cells occupy the largest area on chip and are responsible for significant leakage power consumption in modern microprocessors. With the transition from planar Complementary Metal-Oxide-Semiconductor (CMOS) technology to FinFETs, FinFET SRAM design has become important. However, increasing leakage power consumption of FinFETs due to aggressive scaling, width quantization, read-write conflict, and process variations make FinFET SRAM design challenging. In this article, we show how Multiparameter Asymmetric (MPA) FinFETs can be used to design ultra-low-leakage and robust 6T SRAM cells. We combine multiple asymmetries, namely, asymmetry in gate work function, source/drain doping concentration, and gate underlap, to address various SRAM design issues all at once. We propose five novel MPA FinFET SRAM cell designs and compare them with symmetric and Single-Parameter Asymmetric (SPA) FinFET SRAM cells using dc and transient metrics. We show that the leakage current of MPA FinFET SRAM cells can be reduced by up to 58× while ensuring reasonable read/write stability metric values. In addition, high stability metric values can be achieved with 22× leakage current reduction compared to the traditional symmetric FinFET SRAM cell. There is no area overhead associated with MPA FinFET SRAM cells. ACM Reference Format:Abdullah Guler and Niraj K. Jha. 2016. Ultra-low-leakage, robust FinFET SRAM design using multiparameter asymmetric FinFETs.

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“…Among many variations of MuGFETs, a self-aligned double-gate (DG-MOSFET) structure like fin-shaped FET (FinFET), both gates of which are raised for enhancing the control of channel carriers, attracts a great deal of attention due to an acceptable sub-threshold swing (SS), high trans-conductance, and reasonable shortchannel effect (SCE). 1,2) Recently, Fossum et al 3) proposed a novel DG-MOSFET which has an asymmetric gate structure, as shown in Fig. 1(a), wherein the improved electrical coupling between both gates enhances the I on =I off ratio and further the threshold voltage (V T ) is properly controlled by the n+/p+ polycrystalline silicon (poly-Si) doping concentration.…”

Section: Introductionmentioning

confidence: 99%

Performance Comparison between Asymmetric Polycrystalline Silicon Gate and TiN Gate Fin-Shaped Field Effect Transistors

Kim

Won

2008

jjap

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We report our numerical study on the device performance of an asymmetric polycrystalline silicon (poly-Si) gate fin-shaped field effect transistor (FinFET) and FinFET with TiN metal gate structure. Our numerical simulation revealed that the asymmetric poly-Si FinFET structures and TiN gate FinFET structures exhibits a superior V T tolerance to the conventional FinFET structure with respect to the variation of fin thickness. For instance, the V T tolerance of the asymmetric poly-Si FinFET were 0.02 V while TiN gate FinFET exhibited 0.015 V tolerance for the variation of the fin thickness of 5 nm (from 30 to 35 nm) while the conventional FinFET demonstrates 0.12 V fluctuation for the same variation of the fin thickness. Our numerical simulation revealed that threshold voltage (V T ) can be controlled within À0:1 to þ0:5 V by the varying of doping concentration of the asymmetric poly-Si gate region from 1:0 Â 10 18 to 1:0 Â 10 20 cm À3 .

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Finfet with isolated n+ and p+ gate regions strapped with metal and polysilicon

Cited by 6 publications

References 2 publications

FinFETs: From Devices to Architectures

FinFETs: From Devices to Architectures

Ultra-low-leakage, Robust FinFET SRAM Design Using Multiparameter Asymmetric FinFETs

Performance Comparison between Asymmetric Polycrystalline Silicon Gate and TiN Gate Fin-Shaped Field Effect Transistors

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