Formation of shallow <i>p</i>+<i>n</i> junctions by BF+2 implantation into thin polycrystalline Si films

Lin, Chin-Teng; Juang, Miin‐Horng; Chou, Po-Chien; Cheng, Huang–Chung

doi:10.1063/1.357393

Cited by 5 publications

(2 citation statements)

References 44 publications

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“…After the planarization and the densification, the samples were deposited with thin poly-Si films of about 150 nm by LPCVD at 620 • C. Then, the samples were BF 2 + -implanted at 75 keV to a dose of 5 × 10 15 cm −2 and subsequently annealed at 800 • C for 30 min. By the above scheme that forms junctions at low temperature, shallow p + n junctions with small leakage can be well achieved [12]. Hence, the effect of thermal-induced stress in the STI process can be well clarified.…”

Section: Methodsmentioning

confidence: 99%

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Study of shallow trench isolation technology with a poly-Si sidewall buffer layer

Juang

Chen²,

Jang³

2007

Semicond. Sci. Technol.

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Shallow trench isolation (STI) technology with a poly-Si buffer layer at the trench sidewall has been studied. At the densification temperature of 950 • C, for the samples without using a poly-Si buffer layer, the resulting junction shows a leakage of about 700 nA cm −2 for a diode area of 100 × 100 µm 2 , primarily due to large peripheral junction leakage. The large leakage is ascribed to the defect generation caused by a thermally induced stress near the trench sidewall. The usage of a poly-Si buffer layer in the trench sidewall is found to significantly improve the junction characteristics. As a result, when a 40 nm poly-Si buffer layer is sandwiched between the Si substrate and the trench-fill silicon oxide, the resultant junctions show a leakage of only about 8 nA cm −2 . This result may reflect the considerably reduced thermally induced stress near the trench sidewall. Furthermore, at the densification temperature of 1100 • C, the usage of a poly-Si buffer layer can help to achieve excellent junctions with a leakage smaller than 5 nA cm −2 for a diode area of 100 × 100 µm 2 .

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Section: Methodsmentioning

confidence: 99%

“…The resultant STI structure with a poly-Si buffer layer was illustrated in figure 2. Furthermore, in order to minimize the effect of the implantinduced defects and the annealing temperature on the resultant junction characteristics, the implantation-through-poly-Si (ITP) technique with low-temperature processing was utilized here [12].…”

Section: Methodsmentioning

confidence: 99%

Study of shallow trench isolation technology with a poly-Si sidewall buffer layer

Juang

Chen²,

Jang³

2007

Semicond. Sci. Technol.

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Formation of shallow n+p junctions by phosphorus implantation into thin polycrystalline-Si films on Si substrates and subsequent cobalt silicidation

Juang

Ou-Yang

Lin

et al. 1999

Solid-State Electronics

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Harnessing reverse annealing phenomenon for shallow p-n junction formation

Krasnobaev

Cuomo

Vyletalina

1997

Journal of Applied Physics

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Monocrystalline silicon was implanted with 60 keV fluorine and 20 keV boron ions and annealed. Carrier profile, fluorine and boron redistribution, and the parameters of p+-n junctions were investigated. In ion implanted Si two specific regions were observed in which peculiarities in carrier concentration, resistivity, and F atoms redistribution occurred. It was reasoned that the “under-surface” specific region is enriched with vacancy-type defects while the “amorphous/crystalline (a/c) interface” region is enriched with interstitial type defects. After annealing at a temperature corresponding to the reverse annealing phenomenon, boron atoms were activated in the “under-surface” and deactivated in the “a/c interface” region. The possibility of PMOS transistor fabrication with ultrashallow p+-n junction (60 nm) and low leakage current by F++B+ implantation and low temperature (600–700) °C annealing by using this phenomenon was demonstrated.

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Formation of shallow p+n junctions by BF+2 implantation into thin polycrystalline Si films

Cited by 5 publications

References 44 publications

Study of shallow trench isolation technology with a poly-Si sidewall buffer layer

Study of shallow trench isolation technology with a poly-Si sidewall buffer layer

Formation of shallow n+p junctions by phosphorus implantation into thin polycrystalline-Si films on Si substrates and subsequent cobalt silicidation

Harnessing reverse annealing phenomenon for shallow p-n junction formation

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