FPGA Realization of FIR Filters by Efficient and Flexible Systolization Using Distributed Arithmetic

Meher, Pramod Kumar; Chandrasekaran, S.; Amira, Abbes

doi:10.1109/tsp.2007.914926

Cited by 162 publications

(75 citation statements)

References 16 publications

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“…Note that Xilinx FIR compiler 5.0 supports the multiple channels with only uniform bandwidth and the same coefficients set whereas the proposed FIR filter supports the multiple channels with different bandwidths. It should also be known that the proposed FIR filter can support filtering for 16 channels with a small overhead of only 7 DSP48Es and 5% more slice registers compared to the best of the existing systolic structures [13] whereas the design of [13] supports only the single channel. …”

Section: Results and Performancementioning

confidence: 99%

A low-cost FPGA implementation of multi-channel FIR filter with variable bandwidth

Park

2015

IEICE Electron. Express

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This paper proposes a low-cost implementation of a multichannel FIR filter on FPGA, where each channel can have variable bandwidth and coefficients. New structures of the tapped-delay line and the coefficient bank unit based on time-division multiplexing are proposed. Pipelined adder tree is used to expedite the filtering process without disturbing generation of control signals for multi-channel data access. From implementation results, it is found that the proposed 39-tap FIR filter involves 32% less number of slice registers as well as 65% less number of DSP blocks than the Xilinx FIR Core 5.0, and also supports variable bandwidth.

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Section: Results and Performancementioning

confidence: 99%

A low-cost FPGA implementation of multi-channel FIR filter with variable bandwidth

Park

2015

IEICE Electron. Express

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“…Daitx et al [5] proposed a VHDL approach for designing of optimized FIR filters where the general coefficient representation for the optimal sharing of partial products in multiple constants multiplications is used. Meher et al [6] reported the design optimization of one and two dimensional fully pipelined computing structures for area delay-power-efficient implementation of FIR filter by using the systolic decomposition of distributed arithmetic based inner product computation. The main components of digital FIR filters design on FPGAs are the register bank to save the samples of signals, adder to implement sum operations and multiplier for multiplication of filter coefficients to signal [7].…”

Section: Introductionmentioning

confidence: 99%

“…Similarly, for DA-based (multiplierless) implementation of FIR filters, the memory requirement increases exponentially with the filter order. Hence the complexity of FIR implementation grows with the filter order and the precision of computation; therefore the real-time realization of these filters with desired level of accuracy is a challenging task [6].…”

Section: Introductionmentioning

confidence: 99%

FPGA Implementation of Higher Order FIR Filter

Singh¹,

Prakash

2017

IJECE

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The digital Finite-Impulse-Response (FIR) filters are mainly employed in digital signal processing applications. The main components of digital FIR filters designed on FPGAs are the register bank to save the samples of signals, adder to implement sum operations and multiplier for multiplication of filter coefficients to signal samples. Although, design and implementation of digital FIR filters seem simple but the design bottleneck is multiplier block for speed, power consumption and FPGA chip area occupation. The multipliers are an integral part in FIR structures and these use a large part of the chip area. This limits the number of processing elements (PE) available on the chip to realize a higher order of filter. A model is developed in the Matlab/Simulink environment to investigate the performance of the desired higher order FIR filter. An equivalent FIR filter representation is designed by the Xilinx FIR Compiler by using the exported FIR filter coefficients. The Xilinx implementation flow is completed with the help of Xilinx ISE 14.5. It is observed how the use of higher order FIR filter impacts the resource utilization of the FPGA and it's the maximum operating frequency. Keyword:Fir filter FPGA Higher order fir filter Xilinx

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“…Such solutions can be advantageous in many domains. Among others, in coding standards, where scaling is oriented to variable-size hardware operations, like the Discrete Wavelet Transform (DWT) presented in [2], the variable-size Discrete Cosine Transform (DCT) in [3] or in motion estimation and filters [4], and also, in tasks scaling for multi-standard communication systems [5] and [6].…”

Section: Introductionmentioning

confidence: 99%

“…First, all the proposals are focused on offering solutions to specific problems or applications. Apart from the ones described in this section, other examples of concrete purpose scalable works are the template matching reconfigurable architecture presented in [15], the FIR filter in [4] or the image filter in [7]. Second, the reconfigurable architecture implementations and the design flows do not permit to completely release the area that is not used by the core.…”

Section: Introductionmentioning

confidence: 99%

Generic Systolic Array for Run-Time Scalable Cores

Otero

Krasteva

Torre

et al. 2010

Lecture Notes in Computer Science

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Abstract. This paper presents a scalable core architecture based on a generic systolic array. The size of this kind of cores can be adapted in real-time to cover changing application requirements or to the available area in a reconfigurable device. In this paper, the process of scaling the core is performed by the replication of a single processing element using run-time partial reconfiguration. Furthermore, rather than restricting the proposed solution to a given application, it is based on a generic systolic architecture which is adapted using a design flow which is also proposed. The paper includes a related work discussion, the proposal and definition of a systolic array communication approach, which does not require the use of specific macro structures and permits to achieve higher flexibility, and a design flow used to adapt the generic architecture. Further, the paper also includes an image filter application as a simple use case, along with implementation results for Virtex 5 FPGA.

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FPGA Realization of FIR Filters by Efficient and Flexible Systolization Using Distributed Arithmetic

Cited by 162 publications

References 16 publications

A low-cost FPGA implementation of multi-channel FIR filter with variable bandwidth

A low-cost FPGA implementation of multi-channel FIR filter with variable bandwidth

FPGA Implementation of Higher Order FIR Filter

Generic Systolic Array for Run-Time Scalable Cores

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