Ge wire MOSFETs fabricated by three-dimensional Ge condensation technique

Irisawa, Toshifumi; Numata, T.; Hirashita, N.; Moriyama, Yoshihiko; Nakaharai, Shu; Tezuka, T.; Sugiyama, N.; Takagi, Shinichi

doi:10.1016/j.tsf.2008.08.054

Cited by 26 publications

(23 citation statements)

References 6 publications

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“…Also, the condensed Ge-rich SiGe films are known to produce high density of holes. 6) This is a crucial problem in the Ge condensation process from the viewpoint of the reduction in the leakage current and the threshold voltage control of pFETs using Ge-rich SiGe and/or Ge channel materials.…”

mentioning

confidence: 99%

Deformation Induced Holes in Ge-Rich SiGe-on-Insulator and Ge-on-Insulator Substrates Fabricated by Ge Condensation Process

Hirashita

Moriyama

Nakaharai

et al. 2008

Appl. Phys. Express

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Electrical properties of Ge-rich SiGe-on-insulator (SGOI) and Ge-on-insulator (GOI) structures fabricated by Ge condensation process have been studied. The SGOI and GOI structures for Ge composition, xGe, larger than 0.4 exhibit p-type conduction. The hole density is found to rapidly increase from 1016 to 1018 cm-3 with an increase in xGe during the Ge condensation and to decrease down to low-1017 cm-3 when xGe reaches unity. Analyses of scanning spreading resistance microscopy have directly revealed that the SGOI and GOI structures are highly conductive along the crosshatched slip bands formed during the condensation, meaning that the holes are induced along the slip bands in SGOI and GOI films. As a result, it is concluded that the hole induced during the Ge condensation is strongly associated with the slip band formation.

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mentioning

confidence: 99%

Deformation Induced Holes in Ge-Rich SiGe-on-Insulator and Ge-on-Insulator Substrates Fabricated by Ge Condensation Process

Hirashita

Moriyama

Nakaharai

et al. 2008

Appl. Phys. Express

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“…7 Raman spectra of the Fin region before and after the recrystallization. Table.１ The strain in the Fin region, which was estimated from Tsang's formula [8]. The Ge concentration is determined by EDX analysis.…”

Section: Resultsmentioning

confidence: 99%

“…1(a). The SGOI mesas are then thermally oxidized to enrich the Ge content [8]. During the oxidation, a Ge fraction, x, becomes higher in the narrower region than in the wider region owing to the oxidation on the sidewalls in addition to the oxidation on the top surface.…”

Section: Introductionmentioning

confidence: 99%

Fabrication of defect-free and relaxed Ge-rich SGOI-wire structures for CMOS applications

Oda¹,

Moriyama²,

Ideda³

et al. 2010

Extended Abstracts of the 2010 International Conference on Solid State Devices and Materials

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“…The large VBO between the Si core and SiGe shell can confine and accumulate mobile holes in the SiGe channel with higher hole mobility and stronger gate controllability over the ultrathin channel, with effective electrical isolation from the Si core. From a processing point of view, low‐temperature epitaxy or Ge condensation techniques can be employed to obtain an ultrathin SiGe channel with a seamless heterojunction to minimize the scattering and to obtain the intended VBO .…”

Section: Simulation Approach and Device Structurementioning

confidence: 99%

Si‐core/SiGe‐shell channel nanowire FET for sub‐10‐nm logic technology in the THz regime

Son

Kam

et al. 2019

ETRI Journal

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The p-type nanowire field-effect transistor (FET) with a SiGe shell channel on a Si core is optimally designed and characterized using in-depth technology computeraided design (TCAD) with quantum models for sub-10-nm advanced logic technology. SiGe is adopted as the material for the ultrathin shell channel owing to its two primary merits of high hole mobility and strong Si compatibility. The SiGe shell can effectively confine the hole because of the large valence-band offset (VBO) between the Si core and the SiGe channel arranged in the radial direction. The proposed device is optimized in terms of the Ge shell channel thickness, Ge fraction in the SiGe channel, and the channel length (L g ) by examining a set of primary DC and AC parameters. The cutoff frequency (f T ) and maximum oscillation frequency (f max ) of the proposed device were determined to be 440.0 and 753.9 GHz when L g is 5 nm, respectively, with an intrinsic delay time (τ) of 3.14 ps. The proposed SiGe-shell channel p-type nanowire FET has demonstrated a strong potential for low-power and high-speed applications in 10-nm-and-beyond complementary metal-oxide-semiconductor (CMOS) technology. K E Y W O R D SCMOS technology, high hole mobility, low-power high-speed operation, nanowire FET, SiGe shell channel, sub-10-nm logic technology, valence-band offset . His current research interests include nanoscale CMOS devices, emerging memory devices and array, photonic devices and integrated circuits, and neuromorphic systems.

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Ge wire MOSFETs fabricated by three-dimensional Ge condensation technique

Cited by 26 publications

References 6 publications

Deformation Induced Holes in Ge-Rich SiGe-on-Insulator and Ge-on-Insulator Substrates Fabricated by Ge Condensation Process

Deformation Induced Holes in Ge-Rich SiGe-on-Insulator and Ge-on-Insulator Substrates Fabricated by Ge Condensation Process

Fabrication of defect-free and relaxed Ge-rich SGOI-wire structures for CMOS applications

Si‐core/SiGe‐shell channel nanowire FET for sub‐10‐nm logic technology in the THz regime

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