Hardware approaches to cache coherence in shared-memory multiprocessors, Part 1

Tomašević, Milo; Milutinović, Veljko

doi:10.1109/mm.1994.363067

Cited by 48 publications

(12 citation statements)

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“…Snooping‐based and snarfing‐based coherence protocols for multiprocessor systems show a long history, and numerous improvements have been proposed . With an increasing number of cores, the classical bus‐based approaches become less practical, because memory and communication performance do not scale well with the number of cores.…”

Section: Related Workmentioning

confidence: 99%

A real‐time capable coherent data cache for multicores

Pyka

Rohde

Uhrig

2013

Concurrency and Computation

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In multicore systems, the concurrent access to shared data generates a bottleneck for the system performance. Cache coherence techniques have been introduced to enable fast access while preserving the data coherence, but these coherence protocols are critical in hard real-time systems. Because the frequent inter-cache communication leads to unpredictable interferences between the cores, the system's timing behaviour is hard to analyse. In this paper, we propose a new, hard real-time capable strategy for multicore systems called on-demand coherent cache ODC 2 . The technique is based on marginal hardware extensions compared with noncoherent caches and the use of common synchronisation techniques. ODC 2 provides coherent accesses to cached shared data as well as caching of private data. Because the presented strategy does not induce interferences between local caches, ODC 2 is capable for hard real-time systems. We present an evaluation of performance and scalability of ODC 2 compared with two standard coherence protocols using a bus-based multicore system.

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Section: Related Workmentioning

confidence: 99%

A real‐time capable coherent data cache for multicores

Pyka

Rohde

Uhrig

2013

Concurrency and Computation

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“…This problem has been thoroughly studied in the literature [11] [12] [13]. In our work, a cache system based on the write-broadcasting approach has been developed.…”

Section: B Cache Systemmentioning

confidence: 99%

Optimized communication architecture of MPSoCs with a hardware scheduler: A system view

Zhang

Castrillón

et al. 2010

2010 International Symposium on System on Chip

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With increasing complexity of MPSoCs, efficient runtime management of system resources becomes of vital importance for improving the system performance and energy efficiency. OSIP [1] -an operating system application-specific instruction-set processor -provides a promising solution to this. It delivers high computational performance to deal with dynamic task scheduling and mapping, while still being programmable. However, the distributed computation among the different processing elements introduces complexity to the communication architecture, which tends to become the bottleneck of such systems. In this work, we show a detailed analysis and optimization for the communication architecture of OSIP-based MPSoCs. In particular, the joint effects of OSIP and the communication architecture are investigated from the system point of view.

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“…A review of these protocols was done by Archibal and Baer [4]. Other well-known reviews and studies about existing protocols [16,2,18] show that write-through invalidate is the less efficient protocol in a bus-like interconnect.…”

Section: Related Workmentioning

confidence: 99%

“…Its area overhead does not scale well with a high number of processors. Our work can be adapted to more efficient solutions as one reviewed in [16,2]. Therefore, our work focuses on on-chip shared memory multicore systems with NoC and caches.…”

Section: Introductionmentioning

confidence: 99%

Comparison of memory write policies for NoC based multicore cache coherent systems

Massas

Pétrot

2008

Proceedings of the Conference on Design, Automation and Test in Europe

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The following study shows a direct comparison of memory write policies in Shared Memory Multicore Systems. Although there are much work and many studies about this issue, our work takes into account the difficulties related to on chip communication using network-like interconnects. Our study is based on Cycle Approximate Bit Accurate simulations (CABA) of platforms with up to 64 processors, modelling accurately all the aspects of multi-threaded program execution and memory accesses. Our main resultsshow that write-through caches perform well compared to write-back ones, with a slightly simpler implementation and comparable traffic.

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Hardware approaches to cache coherence in shared-memory multiprocessors, Part 1

Cited by 48 publications

References 0 publications

A real‐time capable coherent data cache for multicores

A real‐time capable coherent data cache for multicores

Optimized communication architecture of MPSoCs with a hardware scheduler: A system view

Comparison of memory write policies for NoC based multicore cache coherent systems

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