High-current failure model for VLSI interconnects under short-pulse stress conditions

Distributed ESD protection for high-speed integrated circuits

“…Typically, up to two times increase in resistance is observed at the onset of metal melting during ESD stress [9]. However, in our design a large metal cross-sectional area is used (36 m ) which is more than three times what is usually recommended [9], [16]. This reduces the temperature increase during ESD stress and the transmission line loss in normal operation.…”

“…In addition, the parallel conduction in the p-FET and the diode of the n-FET results in an effective lowering of the dynamic resistance which is more severe at high current levels. Hence, at extreme stress conditions, the conductance model needs to account for the current-dependent and temperature-dependent resistances [16].…”

On thermal effects in deep sub-micron VLSI interconnects

“…The AT$elf.heating in interconnects given by (8) can be written in terms of the RMS current density as, Here t,,, and W,,, are the thickness and width of interconnect metal line, and p&T,,,) is the metal resistivity at temperature T,. Note that the thermal impedance &nr in (8) has been expressed as,…”

“…For extracting the appropriate value of $, the thermal impedance was experimentally determined using (8), for AlCu interconnects fabricated in a state-of-the-art 0.25~pm industrial CMOS process flow. Results are shown in Fig.…”

“…Hence, temperature rise of metal interconnects due to self-heating phenomenon can also limit the maximum allowed average current density, javg.m;lx, since EM capability is dependent on the average current density [7]. Thirdly, thermally induced open circuit metal failure under short-duration high peak currents including electrostatic discharge (ESD) is also a reliability concern, [8] and can introduce latent EM damage [9] that has important reliability implications.…”