High performance and low power transistors integrated in 65nm bulk CMOS technology

Luo, Zuying; Steegen, An; Eller, M.; Mann, R. W.; Baiocco, Christopher; Nguyen, P.; Kim, L.; Hoinkis, M.; Ku, V.; Klee, Velveth; Jamin, F.; Wrschka, P.; Shafer, P.; Lin, Weijie; Fang, Sunny; Ajmera, A.; Tan, Wee Chong; Park, D.; Mo, R.; Lian, J.; Vietzke, D.; Coppock, C.; Vayshenker, A.; Hook, T.B.; Chan, V.; Kim, K.; Cowley, A.; Kim, S.; Kaltalioglu, E.; Zhang, B.; Marokkey, Sajan; Lin, Yo-Sheng; Lee, K.; Zhu, Hao; Weybright, M.; Rengarajan, R.; Ku, Ja Chun; Schiml, T.; Sudijono, J.; Yang, I.Y.; Wann, C.

doi:10.1109/iedm.2004.1419254

Cited by 39 publications

(28 citation statements)

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“…These results are plotted in Fig. 2.5 and show close-to-ideal characteristics in comparison with the modeling results of double-gated SOI transistors published in [3] and in the previous experimental data [7,[11][12][13][14][15][16][17][18]. Figure 2.6 shows the inverter transfer function produced by the 4 nm radius and 7 nm effective channel length NMOS and PMOS SNTs.…”

Section: Characteristics Of the Selected Nmos And Pmos Transistorssupporting

confidence: 62%

“…These values are an order of magnitude smaller than ΔV T values of the 20 nm gate length bulk silicon transistors reported by Boeuf [8] and others [9][10][11][12]. The amount of DIBL is 114 mV/V for the NMOS and 69 mV/V for the PMOS transistors with 4 nm radius and 7 nm effective channel length.…”

Section: Characteristics Of the Selected Nmos And Pmos Transistorsmentioning

confidence: 58%

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Single Work Function Silicon Nanowire MOS Transistors

Bindal

Hamedi-Hagh

2016

Silicon Nanowire Transistors

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In the first chapter of this book, SNTs with dual work function gates were designed and their device characteristics were examined. Later in the same chapter, basic digital CMOS gates were built; their circuit performance, power dissipation, and layout characteristics were analyzed; basic SNT processing steps were shown. A dual work function CMOS technology requires the use of different metals in NMOS and PMOS transistor gates. Finding the appropriate metals that match exactly to the work function values found in this study may often be a difficult enterprise as it may require alloys for gate material or incompatible metals with the SNT processing.One way to reduce the set of problems associated with dual metals is to use a single metal gate. Therefore, this chapter is dedicated to design NMOS and PMOS transistors with a single work function metal gate, and furthermore use these transistors in designing CMOS circuits.As in Chapter 1, this chapter will also introduce the design criteria for SNTs that use a single metal gate, show the design flow to select optimum device dimensions for both NMOS and PMOS transistors, and analyze speed, power dissipation and layout area characteristics of various CMOS logic gates and mega cells that use these devices.The design criteria for the single work function NMOS and PMOS SNTs are very similar to what has been applied to the dual work function SNTs.1. NMOS and PMOS transistors need to have at least 300 mV threshold voltage for 1 V CMOS circuit operation 2. The static OFF current has to be under 1 pA in either NMOS or PMOS transistor

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Section: Characteristics Of the Selected Nmos And Pmos Transistorssupporting

confidence: 62%

Section: Characteristics Of the Selected Nmos And Pmos Transistorsmentioning

confidence: 58%

Single Work Function Silicon Nanowire MOS Transistors

Bindal

Hamedi-Hagh

2016

Silicon Nanowire Transistors

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“…The devices used in this study are 45 nm low-power CMOS [5,6] and 65 nm CMOS [7] devices from IBM. The 45 nm devices all have a gate length of 40 nm and V DD = 1.1 V, while the 65 nm devices have a gate length of 50 nm and V DD = 1 V. For the 45 nm devices, the device width is increased by either (a) keeping the number of fingers (NF) constant (NF=60) and increasing the unit finger width (WF) from 0.5 μm to 5 μm, or (b) keeping the finger width constant (WF=1.5 μm) and increasing NF from 20 to 120.…”

Section: Technologymentioning

confidence: 99%

RF power potential of 45 nm CMOS technology

Gogineni

Alamo

Putnam

2010

2010 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF)

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− This paper presents the first measurements of the RF power performance of 45 nm CMOS devices with varying device widths and layouts. We find that 45 nm CMOS can deliver a peak output power density of around 140 mW/mm with a peak power-added efficiency (PAE) of 70% at 1.1 V. The PAE and P out decrease with increasing device width because of a decrease in the maximum oscillation frequency (f max ) for large width devices. The PAE also decreases with increasing frequency because of a decrease in gain as the operating frequency approaches f max . The RF power performance of 45 nm devices is shown to be very similar to that of 65 nm devices.

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“…At present the double-gate devices becomes non-planar transistor architectures, which is a solution for sub 45-nm nodes [16][17][18]. The desired switching system must have a simple and low cost structure which can also confine all the improvement of MultipleInput, Multiple-Output (MIMO) systems [19]. This proposed switch is cost effective and able of selecting data streams from the two antennas for transmitting and receiving processes simultaneously.…”

mentioning

confidence: 99%

Analysis of double-gate CMOS for double-pole four-throw RF switch design at 45-nm technology

2011

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In this paper, we have analyzed a 45-nm RF CMOS switch design technology with the double-pole fourthrow circuit by using independently controlled double-gate MOSFET. The proposed switch reduces the number of transistors and increases the logic density per unit area as compare to the conventional CMOS switch. With the unique independent double-gate properties, we have demonstrated the potential advantages in terms of the drain current, threshold voltage, attenuation with ON resistance, flat-band capacitances, charge density and power dissipation of the proposed switch, which provides a switch with a significant drive circuit that is free from the signal propagation delay and additional voltage power supply. Moreover, the main emphasis is to provide a plurality of such switches arranged in a densely configured switch array, which provides a lesser attenuation, and better isolation with fast switching speed.

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High performance and low power transistors integrated in 65nm bulk CMOS technology

Cited by 39 publications

References 0 publications

Single Work Function Silicon Nanowire MOS Transistors

Single Work Function Silicon Nanowire MOS Transistors

RF power potential of 45 nm CMOS technology

Analysis of double-gate CMOS for double-pole four-throw RF switch design at 45-nm technology

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