High-Performance and Robust SRAM Cell Based on Asymmetric Dual-$k$ Spacer FinFETs

Abstract

This paper proposes a new asymmetric underlap Fin-Field Effect Transistor (FinFET) structure using a dual-k spacer. Asymmetric dual-spacer at source shows excellent gate control over the channel due to increase in the outer fringe field at gate/source underlap. Hence, this structure exhibits a superior short-channel effect metric over the conventional/single-spacer underlap FinFET. The proposed asymmetric structure enhances static random access memories (SRAMs) performance in terms of robustness, access times as well as leakage power during the hold, read, and write operations. The hold static noise margin and write margin increases by 5.16% and 5.66%, respectively. The read stability enhances by 13.75% and 19.35% over conventional FinFET SRAM circuit. Furthermore, the leakage power reduces by 60%, and write access time improves by 23.63%. Compared with conventional FinFET-based SRAM, same bit-cell area and read delay are associated with the proposed structure. Supply voltage scalability on SRAM design metrics is also investigated. In addition to SRAM application, underlap length, lateral source/drain doping gradient, and the high-k spacer width are optimized for high-performance digital applications.Index Terms-Access time, dual-spacer, low-power static random access memory (SRAM) cell, read static noise margin (SNM), robustness, underlap FinFET, write ability.

Exploration of symmetric high-k spacer (SHS) hybrid FinFET for high performance application

“…Major manufacturing companies like Intel and TSMC have adopted FinFET in their 22-nm technology node while others are expecting to use it in the near future [1,2]. This advancement in technology facilitates highly energy efficient electronics and a long battery lifetime in both low power (LP) and high performance (HP) operating regions.…”

“…Previously, the underlap FinFETs have already earned very good control over SCEs [13,14]. Similarly, Pal et al [1,2] have proposed that excellent control over channel and significant improvement in I on and I off are achievable with contemplate dual-k spacers in the underlap region. This work quantitatively describes the effect of considering high-k dielectric as spacer materials in the underlap regions of a hybrid FinFET on various performance metrics.…”

Dual Material Pile Gate Approach for Low Leakage Finfet

“…Only then, it was adopted as a major way forward for incorporation within IC technology (Moshgelani et al, 2012). Over the years, there were several changes that FinFET had adopted, such as structures with underlap and overlap regions as reported in various researches (Pal et al, 2013;Pal et al, 2015), and those structures with different gate materials as reported in (Hussain et al, 2010), in relation to the Fin shape and so on. Gate-all-around (GAA) FinFET is one of the most recent developments in the FinFET series having the channel surrounded from all four sides (Singh et al,Chopade & Padole 169 2008).…”

Nanoscale Memory Design for Efficient Computation: Trends, Challenges and Opportunity

“…Substantial amount of research has so far been reported regarding noise margin improvement including Read/Write Noise Margins (RSNM/WSNM), Hold Static Noise margin (HSNM), data retention and yield improvement of SRAM [4][5][6], like P-P-N based 10T SRAM [7], decoupled latch [8], [9] and 5T SRAM cell [10]. Some popular methods include voltage scaling, switching activity reduction, architectural techniques, and device sizing and new device structures [11][12][13][14]. All these work analyze and quantify the impact on cell stability degradation in lifetime circuit performance.…”